msa2020-stratix10

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msa2020-stratix10

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FPGA experiments for the Microsoft Catapult A-2020 (MSA-2020, Intel Stratix 10 1SG280): LED/ISSP GUI, DDR4 EMIF, PCIe DMA (BAR + hip_ast), 100G transceivers, Corundum mqnic NIC

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- - h264_debug.py
  - h264_encode.py
  - h264_pack.py
  - pcie_fix_bridge_window.sh
- - xk264_mem_fpga.v
- - pcie_dma.qpf
  - pcie_dma.qsf
  - pcie_dma.sdc
  - pcie_dma_top.v
- - axil_cdc.v
  - h264_ext_mem.v
  - h264_wrap.v
  - h264_wrap_dc.v
- - gen_yuv.py
  - input.dat
  - out.264
  - tb_h264.v
  - tb_h264_cdc.v
  - tb_h264_dc.v
  - tb_h264_wrap.v
- H264_INTEGRATION.md
- h264enc.qpf
- h264enc.qsf
- jtag_sys.qsys
- led_ctrl.qpf
- led_ctrl.qsf
- led_ctrl.sdc
- led_ctrl.sof
- led_ctrl.v
- led_ctrl_core.v
- led_gui.py
- led_panel.tcl
- make_qsys.tcl
- README.md
- tb_led_ctrl_core.v
- dual_ch_test.py
- gen_ddr_pins.py
- issp_mem_bridge.v
- jtag_sys.qsys
- led_ctrl.qpf
- led_ctrl.qsf
- led_ctrl.sdc
- led_ctrl.sof
- led_ctrl.v
- led_ctrl_core.v
- led_gui.py
- led_panel.tcl
- make_qsys.qpf
- make_qsys.qsf
- make_qsys.tcl
- README.md
- spd_read.py
- tb_issp_mem_bridge.v
- tb_led_ctrl_core.v
- - bar_mem.py
  - pcie_disable_fatal_err.sh
  - pcie_fix_bridge_window.sh
- - iopll_100mhz.ip
  - pcie.ip
  - pcie.tcl
  - reset_release.ip
- - pcie_dma.sof
- - pcie_dma.v
- gen_top.py
- HOST_VALIDATION.md
- pcie_dma.qpf
- pcie_dma.qsf
- pcie_dma.sdc
- README.md
- - e100.qpf
  - e100.qsf
  - gen_atx.tcl
  - gen_atx_cascade.qpf
  - gen_atx_cascade.qsf
  - gen_atx_cascade.tcl
  - gen_atx_cascade2.qpf
  - gen_atx_cascade2.qsf
  - gen_atx_cascade2.tcl
  - gen_atx_corundum.qpf
  - gen_atx_corundum.qsf
  - gen_atx_corundum.tcl
  - gen_atx_corundum_s.qpf
  - gen_atx_corundum_s.qsf
  - gen_atx_corundum_s.tcl
  - gen_atx_slave.qpf
  - gen_atx_slave.qsf
  - gen_atx_slave.tcl
  - gen_atx_slave2.qpf
  - gen_atx_slave2.qsf
  - gen_atx_slave2.tcl
  - gen_fpll.tcl
  - gen_issp.tcl
  - gen_mac.tcl
  - gen_mac_sys.tcl
  - gen_rstrel.tcl
  - probe_mac.qpf
  - probe_mac.qsf
  - probe_mac.tcl
  - probe_mac2.qpf
  - probe_mac2.qsf
  - probe_mac2.tcl
  - qsfp_100g.qpf
  - qsfp_100g.qsf
  - qsfp_100g.sdc
  - qsfp_100g.v
- - _xcvr_inst.vh
  - build_xcvr.tcl
  - gen_phy_ed.tcl
  - make_ips.tcl
  - make_xcvr_sys.tcl
  - prbs31.sv
  - qsfp_prbs.qpf
  - qsfp_prbs.qsf
  - qsfp_prbs.sdc
  - qsfp_prbs.v
  - xcvr_sys.qsys
  - xcvr_test.py
- - gen_issp.qpf
  - gen_issp.qsf
  - gen_issp.tcl
  - gen_rstrel.qpf
  - gen_rstrel.qsf
  - gen_rstrel.tcl
  - retimer_init.qpf
  - retimer_init.qsf
  - retimer_init.sdc
  - retimer_init.v
  - retimer_test.py
- - qsfp_xcvr.qpf
  - qsfp_xcvr.qsf
  - qsfp_xcvr.sdc
  - qsfp_xcvr.v
  - sync_reset.sdc
  - xcvr_test.py
- README.md
- - mqnic.h
  - mqnic_board.c
  - mqnic_dev.c
  - mqnic_ethtool.c
  - mqnic_main.c
- - build_load_mqnic.sh
  - mqnic-dump.txt
- - eth_xcvr_gx.ip
  - eth_xcvr_gx.qpf
  - eth_xcvr_gx.qsf
  - eth_xcvr_gx.tcl
  - eth_xcvr_gx_pll.ip
  - eth_xcvr_gx_pll.qpf
  - eth_xcvr_gx_pll.qsf
  - eth_xcvr_gx_pll.tcl
  - eth_xcvr_gxt.ip
  - eth_xcvr_gxt.qpf
  - eth_xcvr_gxt.qsf
  - eth_xcvr_gxt.tcl
  - eth_xcvr_gxt_buf.ip
  - eth_xcvr_gxt_buf.qpf
  - eth_xcvr_gxt_buf.qsf
  - eth_xcvr_gxt_buf.tcl
  - eth_xcvr_gxt_pll.ip
  - eth_xcvr_gxt_pll.qpf
  - eth_xcvr_gxt_pll.qsf
  - eth_xcvr_gxt_pll.tcl
  - eth_xcvr_reset.ip
  - eth_xcvr_reset.qpf
  - eth_xcvr_reset.qsf
  - eth_xcvr_reset.tcl
  - iopll_100mhz.ip
  - iopll_100mhz.qpf
  - iopll_100mhz.qsf
  - iopll_100mhz.tcl
  - pcie.ip
  - pcie.qpf
  - pcie.qsf
  - pcie.tcl
  - ref_div.ip
  - ref_div.qpf
  - ref_div.qsf
  - ref_div.tcl
  - reset_release.ip
  - reset_release.qpf
  - reset_release.qsf
  - reset_release.tcl
- - qsfp_mqnic.sof
- - eth_xcvr_phy_quad_wrapper.v
  - eth_xcvr_phy_wrapper.v
  - fpga.v
  - fpga_core.v
  - sync_signal.v
- HOST_VALIDATION.md
- pins_a2020.qsf
- qsfp_mqnic.qpf
- qsfp_mqnic.qsf
- qsfp_mqnic.sdc
- README.md
- sources_common.qsf
- sync_reset.sdc
- - bar_mem.py
  - pcie_disable_fatal_err.sh
  - pcie_fix_bridge_window.sh
  - video_accel_test.py
- - iopll_100mhz.ip
  - pcie.ip
  - pcie.tcl
  - reset_release.ip
- - pcie_dma.sof
- - pcie_dma.v
  - video_accel.v
- - tb_video_accel.v
  - tb_video_accel_conv.v
- gen_top.py
- HOST_VALIDATION.md
- pcie_dma.qpf
- pcie_dma.qsf
- pcie_dma.sdc
- README.md
- - dct_test.py
  - pcie_fix_bridge_window.sh
- - iopll_100mhz.ip
  - pcie.ip
  - pcie.tcl
  - reset_release.ip
- - pcie_dma.sof
- - dct_accel.v
  - dct_coef.vh
  - pcie_dma.v
- - fdct.hex
  - idctpix.hex
  - pixin.hex
  - tb_dct.v
- dct_coef.vh
- gen_dct.py
- pcie_dma.qpf
- pcie_dma.qsf
- pcie_dma.sdc
- README.md
- - ddr4_fb_test.py
  - pcie_fix_bridge_window.sh
- - iopll_100mhz.ip
  - pcie.ip
  - pcie.tcl
  - reset_release.ip
- - pcie_dma.sof
- - axil_ddr_bridge.v
  - pcie_dma.v
- - tb_bridge.v
- jtag_sys.qsys
- pcie_dma.qpf
- pcie_dma.qsf
- pcie_dma.sdc
- README.md
- 25G 28G 重定时器与转接驱动器在常见应用中的最优化实现.pdf
- DS280DF810 DS250DF810 在通信系统中的快速编程指南.pdf
- Tile.jpg
- Understanding EEPROM Programming for 25-G to 28-G.pdf
.gitignore
MORNING_ACTION_PLAN.md
README.md
README.zh-CN.md
VIDEO_ACCEL_TOMORROW.md

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**English** | [中文](README.zh-CN.md)

Open-source experiment projects and host-side tools for the decommissioned
datacenter FPGA board **MSA-2020** (Microsoft Catapult A-2020,
Stratix 10 `1SG280LN2F43E2VG`).

## Project List

| # | Project | Contents | Status |
|---|---------|----------|--------|
| **1** | [Blink](1_Blink/) | LED effect engine + ISSP host channel + PC GUI with button control / live readback | ✅ **Flash-and-go**; on-board LED counter blinks steadily |
| **2** | [EMIF](2_EMIF/) | DDR4 memory: EMIF calibration + direct host read/write of 8GB RDIMM, **dual-channel** (DIMM0+DIMM1) | ✅ **Hardware-verified**: both channels calibrate successfully, read/write 16/16 words each pass |
| **3** | [PCIE_DMA](3_PCIE_DMA/) | Standalone minimal PCIe experiment: host reads/writes 256KB on-chip FPGA RAM directly via BAR0 (hip_ast + Corundum TLP stack) | ✅ **Hardware-verified**: host read/write of 256KB BAR; all 65536 unique words / byte enables / boundaries pass |
| **4** | [100GBase_loop](4_100GBase_loop/) | QSFP0 transceiver bring-up + retimer + 100G MAC, loopback verification | ✅ Transceiver 4×25.78G loopback / retimer both **hardware-verified**; ⛔ bonded 100G MAC limited by board design |
| **5** | [Corundum_fork_on_MSA2020](5_Corundum_fork_on_MSA2020/) | Corundum mqnic NIC port (PCIe DMA + 100G) | ✅ **Hardware-verified**: enumeration as 1234:1001 + driver probe + dual ports + DMA queues (Gen2 x8); optical TX/RX pending QSFP module |
| **7** | [video_accel](7_video_accel/) | **Video compute accelerator**: PCIe BAR back-end swapped for a video compute engine, 9 modes (RGB↔YUV / grayscale / invert / AI normalization / threshold / brightness-contrast + 3×3 convolution: blur / sharpen / Sobel / emboss) | ✅ **Hardware-verified**: all 9 modes bit-exact against the software reference, all PASS |
| **8** | [dct_codec](8_dct_codec/) | **8×8 DCT/IDCT transform core** (the transform heart shared by H.264/H.265/JPEG); coefficients generated by `gen_dct.py`, RTL and host reference share the same table | ✅ **Hardware-verified**: FDCT/IDCT bit-exact against reference, round-trip reconstruction succeeds |
| **9** | [ddr4_framebuffer](9_ddr4_framebuffer/) | **PCIe→DDR4 framebuffer**: AXI-Lite↔Avalon clock-crossing bridge driving EMIF (reuses project 2) | 🟡 **Full path runs on hardware**: enumeration + dual-DIMM calibration + ~90% read/write correct; remaining ~10% intermittent read errors = the on-board 150MHz reference clock locks DDR4 at 2400MT/s, leaving insufficient DQS strobe timing margin (not an integration bug; root-caused) |
| **10** | [h264_encoder](10_h264_encoder/) | **Open-source H.264 encoder integration**: port of [openasic-org/xk264](https://github.com/openasic-org/xk264) (Fudan University, complete Baseline encoder) to S10, with a PCIe BAR functional shell (feed YUV → fetch H.264 bitstream) | ✅ **Hardware-verified closed loop**: host writes frame → hardware encodes (50MHz independent clock domain, dual-clock shell `h264_wrap_dc`) → bitstream read back is **byte-identical to the simulation golden** → software packs SPS/PPS → ffmpeg decodes and reconstructs the original image (QP27, Y mean error 0.702). See [H264_INTEGRATION.md](10_h264_encoder/H264_INTEGRATION.md) |

**Projects 7–10 form a video compute accelerator** (image preprocessing + video
filtering + AI pre-processing + codec transforms + framebuffer, all riding on
the already-verified PCIe BAR framework). Workflow: **first simulate with
iverilog against a bit-exact Python reference, then compile in Quartus** —
this flow caught two BRAM read-latency bugs of the same kind (FSM missing a
wait state) before compilation. See [VIDEO_ACCEL_TOMORROW.md](VIDEO_ACCEL_TOMORROW.md)
for the flash-and-test guide.

> **Project 10 debugging war story** (two stacked bugs; broadly useful for any
> "simulation passes, silicon fails" situation):
> ① Non-deterministic encoder output = a hand-written AXI-Lite asynchronous
> clock-domain-crossing handshake with insufficient margin → refactored into a
> **dual-clock true-dual-port BRAM + single-bit synchronizers**
> (`h264_wrap_dc.v`, reads and writes separated in time); the non-determinism
> disappeared.
> ② Still deterministically wrong after the fix (541B vs. 168B in simulation) =
> `cur_mb.v` was missing `` `include "enc_defines.v"``: iverilog/Questa treat
> all files on the command line as **one compilation unit** (macros leak across
> files, so the 64-bit ports were correct), while **Quartus Pro compiles each
> file as an independent compilation unit** → `` `BIT_DEPTH`` undefined → the
> pixel port collapsed to 9 bits. Fix = add `VERILOG_MACRO "BIT_DEPTH=8"` to
> the qsf. The clue had been sitting in the synthesis warnings all along
> (`16735: actual bit length 64 differs from formal bit length 9`) —
> **audit every width-mismatch warning, one by one**.

> **A note on H.264/H.265**: a complete H.264/H.265 codec cannot be hand-written
> from scratch (motion estimation + CABAC + deblocking filter are giant IPs).
> Project 8 delivers its mathematical core, the DCT/IDCT; project 10 integrates
> the real open-source core xk264. **The xk264 sources are NOT included in this
> repository** (its license forbids redistribution — `git clone` it yourself);
> this repository only contains the integration docs, the project qsf, and my
> original FPGA memory library `mem_fpga/` (replacing its ASIC tri-state
> models). H.264 is also covered by the MPEG-LA patent pool; shipping
> commercial products requires a license. For H.265, the only open-source
> hardware is uvgKvazaarHW via an HLS (Catapult) flow — there is no pure-RTL core.

Each project directory is self-contained (Quartus project + RTL + host scripts
+ README). Open each `.qpf` with Quartus Prime Pro 23.3 to compile, or flash
the bundled `.sof` directly. (Project 4 is a collection of sub-projects; see
the README inside its directory.)

## Board Essentials (shared across experiments — hard-won lessons)

- **JTAG limitation**: the on-board FT232H uses a Catapult custom driver
  (`jtag_hw_microsoft_catapult.dll`) that only supports programming and simple
  shifts; System Console's JTAG-Avalon streaming **hangs permanently**.
  All host communication therefore goes through **ISSP** (single-shot shifts),
  measured stable at ~150 ops/sec.
- **VID power configuration** (`PWRMGT_*`, SDM pins) **must** match the
  official blink example — a wrong configuration can destroy the board. Every
  qsf here already includes it; do not modify.
- **DDR4**: **4 independent channels**, DIMM0/1/2/3 ↔ `ddr4_mem[2]/[3]/[0]/[1]`
  (CK pins AP10/L6/AU22/K31); each channel routes only 9 DQS groups + 1 chip
  select → **only 1Rx8 is supported** (x8 devices, single rank), capped at
  2400MT/s. See the 2_EMIF README for dual-channel details.
- **DDR4 calibration root cause** (details in the 2_EMIF README): the RDIMM's
  PAR/ALERT_n must be connected; let the EMIF IP derive the timing parameters
  (TCL/WTCL) automatically — do not lock them by hand.
- Board-level shared I2C: `SCL=AC28 / SDA=AB28` (3.0-V LVTTL), hosting the
  DIMM SPD (0x50), FPC202, DS250DF810 retimer, etc.
- **QSFP0 transceivers** (25.78G GXT): refclk `AD34` (644.53125MHz); TX/RX are
  wired to **non-contiguous physical channels 0,1,3,4** (designed for 4×25G
  independent lanes, not bonded 100G). The correct topology = Corundum
  520N_MX (master ATX + atx_blw buffer + iqclk refclk), `anlg_link=sr`.
  See the READMEs inside projects 4 / 5.
- 100MHz user clock on `PIN_AD6` (1.8V); for the same board also see
  [SuperSodaSea/Plugcat](https://github.com/SuperSodaSea/Plugcat).
- **PCIe**: Gen3 x16, `TX BB34..` / `RX AV30..` / refclk `AM34` / perst `AC26`.

## Host Environment

Windows + Python 3 + Quartus Prime Pro 23.3 (syscon as the JTAG back-end).
On first use, install the FTDI D2XX driver per the board's documentation
package and copy the custom dll into `quartus\bin64`.
(Note: the **NIC driver for project 5 Corundum mqnic is Linux-only**; on
Windows you can only verify PCIe enumeration — see
`5_Corundum_fork_on_MSA2020/HOST_VALIDATION.md`.)

## Roadmap

- [x] 1 LED control + host GUI
- [x] 2 DDR4 EMIF single-channel + **dual-channel** (DIMM0+DIMM1, hardware-verified)
- [x] 4 QSFP0 4×25.78G transceiver loopback (hardware-verified) + retimer (hardware-verified)
- [x] 5 Corundum mqnic port compiles to .sof
- [x] 5 mqnic in a host PCIe slot + Linux driver **hardware-verified** (enumeration + probe + dual ports + DMA queues; kernel 7.0 driver porting patch in its HOST_VALIDATION.md)
- [x] 3 Standalone minimal PCIe experiment: BAR read/write **hardware-verified** (hip_ast + Corundum TLP stack, BAR0 → 256KB on-chip RAM)
- [x] 7 Video compute engine, 9 modes **hardware-verified** (color-space conversion / filtering / AI pre-processing, bit-exact against reference)
- [x] 8 8×8 DCT/IDCT transform core **hardware-verified** (FDCT/IDCT round-trip reconstruction)
- [x] 9 PCIe→DDR4 framebuffer full path **runs on hardware** (dual-DIMM calibration + ~90%; remaining 10% = read timing margin at 2400MT/s, constrained by the on-board 150MHz reference clock)
- [x] 10 Open-source H.264 encoder xk264 **synthesizes** on S10
- [x] 10 H.264 encoder PCIe functional shell **hardware-verified closed loop** (feed YUV → encode → bitstream byte-identical to simulation golden → ffmpeg decodes and reconstructs the original image)
- [ ] 2 DDR4 four-channel extension (DIMM2/DIMM3, same approach applies)
- [ ] 4 bonded 100G MAC (limited by board design, under exploration)
- [ ] 5 mqnic actual packet TX/RX on the optical ports (needs QSFP28 modules / loopback plugs)
- [ ] 9 DDR4 framebuffer at 100% (constrained by the 150MHz reference clock locking 2400MT/s; possible directions: Read DBI / on-chip framebuffer)
- [ ] 10 H.264 higher-resolution support (grow the input/output BRAMs or hook the ext_ reference frames to DDR4; currently verified at 96×64 intra-only)

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