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Open-source SystemVerilog simulator in Rust. 4-state, event-driven, IEEE 1800-2023, runs real UVM.

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Download Latest Version (.zip)

- - msrv.yml
  - test.yml
- - gen_designs.cpython-312.pyc
- - b1_comb_mesh.sv
  - b2_pipeline.sv
  - b3_memory.sv
  - b4_oop_tb.sv
  - b5_elab_scale.sv
  - README.md
  - run_crosstool.sh
- - b2_vm_dispatch.sv
  - b2b_vm_branchy.sv
  - b3_mem_sweep_10.sv
  - b3_mem_sweep_12.sv
  - b3_mem_sweep_14.sv
  - b3_mem_sweep_16.sv
  - b3_mem_sweep_18.sv
  - b3_mem_sweep_20.sv
  - b3_mem_sweep_22.sv
  - b5_constraint_rand.sv
- gen_designs.py
- README.md
- run_bench.sh
- run_uvm_bench.sh
- summarize.py
- - xezim_runner.py
- ast_shared_stmt_lists_scope.md
- DEBUGGING.md
- dpi-guide.md
- perf_dump_offload_2026-07-28.md
- uvm-guide.md
- Xezim_Module_Timescale_LRM_Extension.pdf
- Xezim_Module_Timescale_User_Guide.pdf
- - .gitignore
  - link.ld
  - Makefile
  - README.md
  - test_spike_asm.S
  - test_spike_dpi.sv
  - xezim_spike_dpi.cpp
  - xezim_spike_dpi.svh
- e902_part1_ibuf.v
- e902_part2_ifctrl.v
- e902_part3_iu_stall.v
- e902_part4_decd_probe.v
- e902_part5_decd_min.v
- e902_part6_decd_replay.v
- e902_part7_ifctrl_replay.v
- full_adder.sv
- perlp_toy.sv
- stress_comb.sv
- stress_explicit.sv
- stress_signals.sv
- tb_adder.sv
- test.sv
- test2.sv
- test3.sv
- sv_vpi_user.h
- svdpi.h
- uvm_dpi_xezim.cc
- veriuser.h
- vpi_user.h
- code.css
- details-view.css
- filter.js
- getting-verilator-started-with-uvm.md
- log.css
- report.css
- report.js
- sv-tests-compliance.md
- svtests_index.html
- svtests_report.csv
- build_uvm_dpi.sh
- cargo-local.sh
- fst-repair-timetable.py
- install_xezim_on_mac.sh
- Makefile
- run_cv32e40p_uvm.sh
- use-local-core.sh
- - mspec.html
  - README.md
  - run_c910_hello.sh
  - run_c910_hello_xtrace.sh
  - setup.sh
  - vspec.html
  - xuantie_c910.html
- - bench.rs
- - aot.rs
  - arena.rs
  - bytecode.rs
  - dispatch.rs
  - fst_sink.rs
  - jit.rs
  - mod.rs
  - simulator.rs
  - soa.rs
- - tests.rs
- benchw.rs
- build.rs
- env_vars.rs
- intra_delay.rs
- lib.rs
- main.rs
- multikernel.rs
- report.rs
- should_fail_lint.rs
- vpi_printf_shim.c
- - array_equality_class.rs
  - assoc_enum_key_class_property.rs
  - assoc_typedef_element_class.rs
  - bit_class_property_signedness.rs
  - blocking_task_super_dispatch.rs
  - class_field_named_event.rs
  - class_formal_typedef_widen.rs
  - class_handle_return_preservation.rs
  - class_init_cast_copy.rs
  - class_local_typedef_aa.rs
  - class_local_typedef_resolution.rs
  - class_localparam_array.rs
  - class_method_dispatch.rs
  - class_name_method_shadow.rs
  - class_output_handle_copyback.rs
  - class_packed_and_type_params.rs
  - class_param_siblings.rs
  - class_program_test.rs
  - class_property_packed_selects.rs
  - class_property_param_width.rs
  - class_scoped_enum.rs
  - class_type_param_properties.rs
  - class_unpacked_struct_properties.rs
  - class_unpacked_struct_property.rs
  - class_value_params.rs
  - class_width_copy_fork.rs
  - collection_of_handles_new.rs
  - constraint_algebra_inherit.rs
  - constraint_array_sum.rs
  - constraint_arrays_ordering.rs
  - constraint_dyn_size_pinned_scalar.rs
  - constraint_foreach_and_casts.rs
  - constraint_funcs_aggregates.rs
  - constraint_inline_enclosing_scope.rs
  - constraint_logical_or.rs
  - constraint_prefixed_inline_with.rs
  - constraint_randc_soft_local.rs
  - cov_covergroup_basic.rs
  - coverage_auto_bins.rs
  - covergroup_coverage_query.rs
  - ctor_dispatch_and_p_format.rs
  - enum_local_shadows_flat_maps.rs
  - factory_run_test.rs
  - fixed_member_pattern_write.rs
  - generate_and_class_parameters.rs
  - inherited_static_shared.rs
  - inspect_class.rs
  - instance_class_comb_and_constraint_scope.rs
  - instance_struct_member_and_class_param.rs
  - issue35_mixed_sign_constraints.rs
  - issue4_coupled_constraints.rs
  - ivtest_class_struct_cluster.rs
  - localparam_class_not_parameterized.rs
  - member_collection_runtime_class.rs
  - method_default_this_call.rs
  - module_scope_derived_constraints.rs
  - module_scope_handle_access.rs
  - nd_array_properties_and_foreach_constraints.rs
  - nested_and_extends_spec.rs
  - nonvirtual_dispatch_fscanf_process.rs
  - nopack_member_array.rs
  - null_deref_fatal.rs
  - out_of_class_method_shadow.rs
  - param_typedef_ctor_resolution.rs
  - process_class_9_7.rs
  - pure_sv_phase_objection.rs
  - randomize_inside_range.rs
  - randomize_member_subset.rs
  - randomize_obj_array_property.rs
  - scope_randomize_dist_and_foreach.rs
  - shadowed_property_storage.rs
  - static_assoc_struct_pool.rs
  - std_randomize_struct.rs
  - string_method_shadows_class_method.rs
  - struct_formal_and_config_foreach.rs
  - struct_output_formal.rs
  - struct_output_inout_ref_formal.rs
  - struct_prop_whole_copy.rs
  - struct_with_class_handle.rs
  - subroutine_local_unpacked_structs.rs
  - super_property_access.rs
  - this_chain_edge_sensitivity.rs
  - type_param_struct_formal.rs
  - typedef_extends_cast.rs
  - typename_param_class.rs
  - unpacked_struct_class_property_whole_value.rs
  - uvm_config_db_tests.rs
  - uvm_factory_linkage.rs
  - uvm_genuine_2017.rs
  - uvm_integration_tests.rs
  - uvm_objection_bridge.rs
  - uvm_printer_fixes.rs
  - vif_property_named_like_instance.rs
  - vif_static_roundtrip.rs
  - virtual_iface_this_binding.rs
- - array_element_collection.rs
  - array_locator_and_reduction.rs
  - array_locator_index.rs
  - array_locator_named_iterator.rs
  - array_of_collections.rs
  - array_of_queues.rs
  - assoc_compliance.rs
  - assoc_method_dispatch.rs
  - assoc_of_struct.rs
  - collection_write_open_gaps.rs
  - concurrent_local_dyn_arrays.rs
  - constant_array_index_dependency.rs
  - cont_assign_2d_array_index0.rs
  - dyn_array_loop_write_notifies.rs
  - dyn_array_of_mailboxes.rs
  - fixed_array_member_initializer.rs
  - fixed_array_member_pattern_forms.rs
  - foreach_blocking_resume.rs
  - foreach_live_size_bounds.rs
  - foreach_negative_dims.rs
  - lrm_clause7_arrays.rs
  - mailbox_bounded.rs
  - multidim_assoc_array.rs
  - noparen_array_methods.rs
  - pp_queue_slice.rs
  - property_queue_and_context.rs
  - queue_dyn_write_semantics.rs
  - queue_local_shadow_restore.rs
  - queue_member_init.rs
  - queue_ops_and_dist.rs
  - sort_with_clause.rs
  - stream_justify_assoc_default_partsel.rs
  - string_foreach_content.rs
  - struct_collections_across_calls.rs
  - void_cast_queue_ops.rs
  - whole_array_continuous_assign.rs
- - child_module_import.c
  - child_module_import_test.sv
  - export_roundtrip.c
  - export_roundtrip_test.sv
  - extended_dpi.c
  - extended_dpi_test.sv
  - force_release_compliance.sv
  - logic_vec_dpi.c
  - logic_vec_dpi_test.sv
  - open_array_dpi.c
  - open_array_dpi_test.sv
  - scalar_types.c
  - scalar_types_test.sv
  - shortreal_string_dpi.c
  - shortreal_string_dpi_test.sv
  - simple_dpi.c
  - simple_dpi_test.sv
  - type_mappings.c
  - type_mappings_test.sv
  - typedef_dpi.c
  - typedef_dpi_test.sv
  - uvm_dpi_test.c
  - uvm_dpi_test.sv
  - vpi_backdoor_compliance.c
  - vpi_backdoor_compliance.sv
  - vpi_conformance.c
  - vpi_conformance.sv
  - vpi_object_model.c
  - vpi_object_model.sv
  - vpi_systf.c
  - vpi_systf.sv
  - vpi_timed_cbs.c
  - vpi_timed_cbs.sv
- - assign_pattern_aggregate.rs
  - drive_strength_pull.rs
  - dump_formats_agree.rs
  - dump_merged_sv.rs
  - fst_roundtrip.rs
  - fst_time_table_breakeven.rs
  - interrupt_finalizes_dumps.rs
  - specify_flags.rs
  - tran_and_implicit_nets.rs
  - udp_primitives.rs
  - vcd_lrm_compliance.rs
- - array_of_module_instances.rs
  - bind_directive_basic.rs
  - bind_in_module.rs
  - bind_path_through_library_module.rs
  - bind_through_nested_part_select.rs
  - bind_upward_refs.rs
  - c910_scoped_cont_assign.rs
  - downward_hier_refs_in_siblings.rs
  - dump_merged_sv_library_dedup.rs
  - dump_merged_sv_top_pruning.rs
  - final_blocks_hierarchy.rs
  - foreach_in_inlined_child.rs
  - foreach_over_submodule_array.rs
  - generate_scope_names.rs
  - generic_interface_ports.rs
  - iface_port_params.rs
  - ifu_ibuf_32_instances_c910.rs
  - implicit_net_gate_port.rs
  - implicit_net_submodule.rs
  - interface_array_element_ports.rs
  - interface_default_clocking.rs
  - ivtest_port_cluster.rs
  - library_dir_on_demand.rs
  - local_method_static_binding.rs
  - modport_shape_battery.rs
  - module_timescale_cli.rs
  - multi_instance_scope.rs
  - multiple_top_modules.rs
  - nested_cross_module_call.rs
  - nested_interface_struct_ports.rs
  - nested_modules_and_zpad.rs
  - nonansi_modport_port_decl.rs
  - nonansi_port_completion.rs
  - nonansi_ports_and_vif_accessors.rs
  - null_ports_lib_defines_nowarn.rs
  - package_scoped_vars_and_methods.rs
  - packed_port_formal_type.rs
  - param_typedef_instance_isolation.rs
  - pct_m_block_scope.rs
  - percent_m_scope.rs
  - pkg_subroutines_and_unit_scope.rs
  - port_net_driven_from_inside.rs
  - repro_import.rs
  - resource_pool_scope_lookup.rs
  - same_name_port_hop.rs
  - submodule_net_array_shapes.rs
  - submodule_two_dim_array_element.rs
  - typedef_array_ports_in_children.rs
  - unpacked_struct_port.rs
  - vif_arrays_and_null_default.rs
  - vif_clocking_in_methods.rs
  - vif_in_subroutines.rs
  - wildcard_import_shadow.rs
- - 00_basic_cons_checks.sv
  - 01_basic_cons_checks.sv
  - 02_basic_cons_checks.sv
  - 03_basic_array_rand.sv
  - 04_sys_user_funcs_in_cons.sv
  - 05_complex_class_struct_union_enum.sv
  - 06_advanced_class_inherit_misc_rand.sv
  - 07_advanced_qaarr_uniq_var_order.sv
  - 08_cons_guard_soft_cons.sv
  - 09_loc_scope_dyn_wt_inline_cons_chk.sv
  - 10_std_randomize_checks.sv
  - 11_rand_func_stability_srandom.sv
  - 12_rand_func_stability_randstate.sv
- - constraint.foreach.sv
  - constraint.typecast.sv
  - data.to.string.fmt.sv
  - dyn.arr.of.mbox.sv
  - final.blocks.test.case.sv
  - fmt.specifiers.sv
  - mbox_in_interface.sv
  - static.init.sysfuncs.sv
  - string.compliance.tests.sv
  - timescale.handling.sv
  - type-parameter-compliance.sv
- - t01_status_running.sv
  - t02_status_finished.sv
  - t03_kill.sv
  - t04_await.sv
  - t05_suspend_resume.sv
- - str_param_spec.sv
- - ch10_assignments.sv
  - ch11_operators.sv
  - ch12_procedural.sv
  - ch13_subroutines.sv
  - ch15_18_20.sv
  - ch6_types.sv
  - ch7_aggregates.sv
  - ch7b_packed_scope.sv
  - ch7c_local_typedef.sv
  - ch8_classes.sv
  - ch9_processes.sv
- - ch14_19_clk_cov.sv
  - ch16_assertions.sv
  - ch21_fileio.sv
  - ch22_preproc.sv
  - ch25_26_ifc_pkg.sv
  - ch5_lexical.sv
  - ch7_11_13_deep.sv
- - ch18_deep.sv
  - ch20_misc.sv
  - ch23_24_hier.sv
- - aot_native_paths.rs
  - array_elem_fast_write.rs
  - array_element_semantics.rs
  - artifact_compression_modes.rs
  - assign_z_passthrough.rs
  - assoc_class_new_stores_instance.rs
  - assoc_dotted_key.rs
  - audit_round45_finds.rs
  - audit_round46_finds.rs
  - audit_sibling_fixes.rs
  - bare_method_call_returns.rs
  - bare_randomize_solver.rs
  - base1_packed_index.rs
  - bind_upward_refs.rs
  - blocking_task_call.rs
  - c910_create_en_cont_assign.rs
  - c910_create_en_full_path.rs
  - call_returned_handle_assoc.rs
  - case_default_arm.rs
  - chained_member_access.rs
  - child_decl_init_and_wide_rand.rs
  - class_collection_storage.rs
  - class_queue_locators.rs
  - clocked_loop_case_nest_compiled.rs
  - comb_regvar_loop_fallback.rs
  - comb_regvar_loop_fallback_dut.sv
  - compliance_tests.rs
  - cov_assertion_basic.rs
  - dead_giant_declaration_elision.rs
  - delay_precision.rs
  - dep_reg_entry_synth.rs
  - deposit_task.rs
  - duplicate_decl_locations.rs
  - edge_and_delay_select_fixes.rs
  - edge_task_call_process.rs
  - elaboration_runaway_guards.rs
  - env_var_registry.rs
  - escaped_identifier_matches_nonescaped.rs
  - factory_register_reentrant.rs
  - force_assign_override_restore.rs
  - force_release_semantics.rs
  - forever_break_continue.rs
  - fresh_audit_finds.rs
  - function_return_bit_select.rs
  - hier_force_holds_against_drivers.rs
  - hier_iface_task_suspension.rs
  - hier_port_drive_and_collision.rs
  - iface_functions_and_vif_locals.rs
  - ifu_ibuf_casez_dispatch_c910.rs
  - ifu_ibuf_create_ptr_rotate.rs
  - ifu_ibuf_entry_pop_c910.rs
  - ifu_precode_c910_pc710.rs
  - implicit_static_diagnostic.rs
  - indexed_event_roundtrip.rs
  - inspect_types.rs
  - issue30_runner.rs
  - issue_cases_runner.rs
  - ivtest_ce_cluster.rs
  - ivtest_misc_cluster.rs
  - ivtest_round55_pins.rs
  - ivtest_tail2_cluster.rs
  - ivtest_tail_cluster.rs
  - library_flags.rs
  - log_redirect.rs
  - loop_body_inlines_pure_call.rs
  - lrm_audit2_runner.rs
  - lrm_audit3_runner.rs
  - lrm_audit_runner.rs
  - lrm_clause10_patterns.rs
  - lrm_clause11_operators.rs
  - lrm_clause13_subroutines.rs
  - lrm_pattern_matching.rs
  - macro_directive_prefix_names.rs
  - mailbox_method_blocking.rs
  - method_call_chaining.rs
  - monitor_on_change.rs
  - monitor_percent_m_scope.rs
  - negative_lsb_range_select.rs
  - nested_struct_string_member_display.rs
  - new_ctor_vs_shallow_copy.rs
  - nonansi_function_args.rs
  - nonzero_lsb_indexed_part_select.rs
  - obj_assocd_event_disable_fork.rs
  - operators_11_select_reduce.rs
  - package_const_fn_params.rs
  - package_property_assertions.rs
  - packed_elem_fn_inline.rs
  - param_class_cast_type_args.rs
  - param_dim_array_nba.rs
  - param_pair_this_type_cast.rs
  - parser_gaps2.rs
  - parser_stmt_gaps.rs
  - pattern_replication_and_extends_args.rs
  - port_width_mismatch_explains.rs
  - preprocessor_directives.rs
  - proc_fsm.rs
  - process_status_name.rs
  - program_block_reactive.rs
  - property_bare_new_initializer.rs
  - property_new_initializer.rs
  - prtest_runner.rs
  - queue_ref_formal_shadowing.rs
  - randcase_randsequence_weights.rs
  - random_stability.rs
  - recursive_function_in_continuous_assign.rs
  - ref_args_alias.rs
  - ref_struct_queue_and_local_shadow.rs
  - reg3456_pure_sv.rs
  - reg4712_visitor_traversal.rs
  - region_fusion.rs
  - repeat_blocking_call.rs
  - replicate_and_pattern.rs
  - resource_pool_fixes.rs
  - sanity_tests.rs
  - sched_trace_orders_a_time_slot.rs
  - severity_exit_status.rs
  - shadow_name_matrix.rs
  - sim_tests.rs
  - single_eval.rs
  - size_test.rs
  - spec_canonical_keying.rs
  - spec_static_and_pkg_queue.rs
  - static_collection_per_spec.rs
  - static_init_sysfuncs.rs
  - static_local_per_spec.rs
  - static_local_scope_isolation.rs
  - static_method_via_handle.rs
  - static_property_access.rs
  - stress_tests.rs
  - struct_arrays_and_interface_members.rs
  - struct_local_declinit_copy.rs
  - super_method_dispatch.rs
  - sv2023_compliance_runner.rs
  - sv_compliance_runner.rs
  - sv_logic_implication.rs
  - sva_action_firing.rs
  - sva_preponed_sampling.rs
  - svtb_suite.rs
  - symbol_clash_checks.rs
  - timescale.rs
  - trireg_charge_and_g_audit.rs
  - two_state_island_coverage.rs
  - unpacked_struct_in_instance.rs
  - unsized_literal_keeps_its_digits.rs
  - uvm_agent_active_config.rs
  - uvm_dpi_builtins.rs
  - value_trace.rs
  - warm_cache_diag_replay.rs
  - while_continue_final_iter.rs
  - x_warn_switch.rs
  - xselect_and_concat_flatten.rs
- - bench_host_workloads.rs
  - cipher_shape_regression.sv
  - design_shape_regression.rs
  - packed_matrix_regression.sv
  - packed_matrix_workload.rs
  - packed_record_edge.sv
  - packed_record_edge_loop.rs
  - report_stats.rs
  - riscv_shape_regression.sv
  - work_counters.rs
- - pr1000.v
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  - pr860.v
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  - pr903.v
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  - pr905.v
  - pr910.v
  - pr913.v
  - pr923.v
  - pr938.v
  - pr938b.v
  - pr938b_std.v
  - pr941.v
  - pr973.v
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  - pr979.v
  - pr985.v
  - pr987.v
  - pr990.v
  - pr991.v
  - pr993.v
  - pr995.v
  - prng.v
  - program2.v
  - program2b.v
  - program3.v
  - program3a.v
  - program3b.v
  - program4.v
  - program5a.v
  - program5b.v
  - program_hello.v
  - program_hello2.v
- - active_region_fifo.rs
  - adaptive_edge_skip.rs
  - always_comb_sensitivity_audit.rs
  - always_iff_guard.rs
  - always_level_delay.rs
  - assoc_bracket_keys.rs
  - audit_ports_disable_drivers.rs
  - bare_clocking_event.rs
  - bare_randomize_in_method.rs
  - bare_randomize_in_method.sv
  - block_local_decl_ast_fallback.rs
  - blocking_loop_break_continue.rs
  - c910_biu_bresp_capture_race.rs
  - c910_settle_miri.rs
  - case_wait_in_task.rs
  - class_event_member_wait.rs
  - class_method_delay_timeunit.rs
  - clock_gate_fanout.rs
  - clock_t0_variable_delay_phase.rs
  - clockgen_x_clock_stays_x.rs
  - clocking_event_cycle_delay.rs
  - comb_collection_element_sensitivity.rs
  - comb_result_clobbered_by_process.rs
  - comb_self_member_sensitivity.rs
  - compiled_for_loops.rs
  - computed_edge_expressions.rs
  - dead_clock_watchdog.rs
  - delay_spike_warning.rs
  - determinism_and_stall.rs
  - disable_loop_label.rs
  - edge_delivery.rs
  - edge_event_lsb.rs
  - event_control_iff_guard.rs
  - event_features_15_5.rs
  - event_triggered_in_event_control.rs
  - event_wait_same_time.rs
  - explicit_sensitivity_and_delay_task.rs
  - finish_with_live_fork_child.rs
  - forever_break_and_disable_fork_label.rs
  - fork_automatic_capture.rs
  - fork_children_start_in_spawn_slot.rs
  - fork_join_edge.rs
  - fork_join_none_await_context.rs
  - fork_var_sharing.rs
  - gap_fixes_scoping_and_nba.rs
  - gate_rise_fall_delay.rs
  - intra_assignment_delay.rs
  - ivtest_always_cluster.rs
  - local_arrays_and_edge_always.rs
  - loop_control_and_oob_index.rs
  - lrm_disable.rs
  - lrm_name_collapse_and_delay.rs
  - mailbox_blocking_processes.rs
  - mailbox_fork_phase_hop.rs
  - multidim_assoc_struct_copy.rs
  - named_event_identity.rs
  - nba_after_zero_delay.rs
  - nba_fast_vs_queue_order.rs
  - nba_index_freeze_and_elem_selects.rs
  - nba_intra_event_control.rs
  - nba_leak_waiter_active_region.rs
  - nba_region_not_flushed_mid_edge.rs
  - nested_delay_slot_servicing.rs
  - null_mailbox_and_stall_location.rs
  - oracle_timing_semantics.rs
  - parallel_dispatch_expr_fallback.rs
  - phase_jump_static_latch.rs
  - phase_jump_static_latch.sv
  - preprocessor_diagnostic_location.rs
  - preprocessor_github_issues.rs
  - procedural_loop_stall.rs
  - procedural_loop_stall.sv
  - process_block_local_shadowing.rs
  - pure_inline_loop_body.rs
  - ranged_port_connections_and_nba_freeze.rs
  - sampled_value_inferred_clock.rs
  - sequential_event_waits.rs
  - specify_delays_and_event_list.rs
  - star_sensitivity_and_implicit_port_net.rs
  - static_local_nba_per_instance.rs
  - static_recursion_shared_cell.rs
  - static_recursion_shared_cell.sv
  - struct_member_read_sensitivity.rs
  - suspending_loop_depth_and_continue.rs
  - task_body_delay_scaling.rs
  - timing_check_delayed_nets_singlelimit.rs
  - typeparam_pool_wait.rs
  - unbased_unsized_fill.rs
  - vardelay_clock_period.rs
  - wait_fork_immediate_children.rs
  - wait_in_foreach_blocks.rs
  - waiter_cont_anyedge_wake.rs
  - waiter_edge_ordering.rs
  - xtrace_conformance.rs
  - zero_delay_inactive_region.rs
- - assoc_in_always_ff_and_string_element_methods.rs
  - call_time_defaults_and_string_queries.rs
  - compiled_sformatf_native.rs
  - display_only_always.rs
  - dpi_child_module_import.rs
  - dpi_integration_tests.rs
  - fixed_string_array_dims.rs
  - format_lrm_compliance.rs
  - format_sibling_fixes.rs
  - fwrite_mcd_fd.rs
  - hierarchical_string_method.rs
  - interface_event_and_submodule_string.rs
  - local_string_dynamic.rs
  - lrm_string_methods.rs
  - native_string_ops.rs
  - nba_last_write_wins_elision.rs
  - nested_fork_shared_write.rs
  - nonzero_lsb_part_select_write.rs
  - p_format_assoc.rs
  - p_format_named.rs
  - p_format_recursive.rs
  - ref_arg_assoc_writeback.rs
  - ref_arg_collection_writeback.rs
  - string_eq_relational_2state.rs
  - string_index_ref_queue.rs
  - string_is_dynamic.rs
  - string_methods_lrm.rs
  - string_property_shadowed_by_local.rs
  - string_returning_fn_inline.rs
  - system_task_gaps.rs
- - Make.svsim
  - Makefile
  - manifest.csv
  - negative_manifest.csv
  - README.md
  - transcript
- - .gitignore
  - packed_port_elem_select.sv
  - packed_port_formal_width.sv
  - packed_port_loop_select.sv
  - param_static_park.sv
  - pct_m_hier_scope.sv
  - run.sh
- - ansi_port_name_with_unpacked_dim.rs
  - array_element_declared_signedness.rs
  - array_parameter.rs
  - array_query_multidim_packed.rs
  - array_read_unknown_index_is_x.rs
  - array_reduction_element_type.rs
  - ascending_indexed_part_select.rs
  - assoc_enum_key_name.rs
  - assoc_keys_and_handles.rs
  - assoc_of_queue_enumeration.rs
  - bits_of_signal_in_const_expr.rs
  - bits_of_type_operands.rs
  - bits_package_scoped_type_width.rs
  - block_local_width_in_index_shift.rs
  - byte_local_narrow.rs
  - callback_typedef_static.rs
  - case_jump_dispatch.rs
  - case_mask_jump_dispatch.rs
  - case_wildcard_signed_extension.rs
  - cast_typeparam.rs
  - cast_valparam_typeparam_static.rs
  - cast_value_param_specs.rs
  - circular_typedef_diagnostics.rs
  - conditional_real_x_select.rs
  - const_function_params.rs
  - constructor_new_not_static.rs
  - constructor_new_property_type.rs
  - constructor_typedef_dispatch.rs
  - copy_constructor_decl_init.rs
  - copy_ctor_type_mismatch.rs
  - declared_signedness_wins.rs
  - decode_helper_assign_compiles.rs
  - default_assignment_pattern_packed.rs
  - defparam_override.rs
  - diag_kind_limit_env.rs
  - dollar_lvalue_and_assoc_width.rs
  - enum_name_formal_param.rs
  - enum_next_prev_count.rs
  - enum_signedness_and_pkg_scope.rs
  - enum_xz_and_package_shapes.rs
  - expression_event_controls.rs
  - force_expression_tracks.rs
  - formal_metadata_shadow_roundtrip.rs
  - formal_type_metadata_and_typedef_packed_array.rs
  - forward_referenced_parameter.rs
  - forward_typedef_class_handle_width.rs
  - function_return_width.rs
  - generate_scope_struct_metadata.rs
  - hierarchy_and_type_overrides.rs
  - implicit_port_net_and_packed_typedef_array.rs
  - inside_const_members.rs
  - inside_defaults_and_foreach_dir.rs
  - instance_queue_structs_and_loop_scope.rs
  - ivtest_cast_cluster.rs
  - lexical_string_literal_semantics.rs
  - local_localparam_width.rs
  - local_packed_struct_alias.rs
  - lrm_dynamic_cast.rs
  - lrm_real_cast_case_inside.rs
  - lrm_struct_union_dims.rs
  - module_type_param_behavioral.rs
  - multi_dim_elem_read_and_param_dims.rs
  - nested_dynamic_members.rs
  - nested_packed_struct_array_access.rs
  - nested_packed_typedefs.rs
  - nonzero_based_vector_reads.rs
  - nonzero_based_vector_writes.rs
  - package_scope_resolution.rs
  - package_typedef_scoping.rs
  - packed2d_slice_ca_offset.rs
  - packed_2d_element_in_size_cast.rs
  - packed_2d_net_element_assign.rs
  - packed_3d_chained_select.rs
  - packed_array_typedef_element_width.rs
  - packed_assignment_patterns.rs
  - packed_elem_shift_context_width.rs
  - packed_element_range_select.rs
  - packed_member_self_determined_width.rs
  - packed_multidim_unpacked_select.rs
  - packed_multilevel_and_collision.rs
  - packed_struct_array_elem_write.rs
  - packed_struct_formal_member.rs
  - packed_struct_pattern_compile.rs
  - param_cb_isolation.rs
  - param_const_eval_contexts.rs
  - param_signedness_and_generate_scope.rs
  - param_sized_array.rs
  - param_struct_widths_and_nba_patterns.rs
  - parameter_const_eval_corners.rs
  - pattern_params_and_call_member.rs
  - power_operator_signedness.rs
  - preprocessor_include_fatal.rs
  - procedural_loop_and_static_fn.rs
  - procedural_storage_semantics.rs
  - property_value_param_binding.rs
  - range_select_param_arith.rs
  - real_literal_comb_eval.rs
  - real_valued_delay.rs
  - shift_context_width.rs
  - shift_width_and_scope_hint.rs
  - signedness_and_power_context.rs
  - size_cast_context_and_fn_return_default.rs
  - star_vs_always_comb.rs
  - static_typedef_singleton.rs
  - streaming_and_typedef_array_width.rs
  - struct_copy_and_queue_ops.rs
  - struct_named_patterns.rs
  - struct_port_pattern_ca.rs
  - struct_real_member_roundtrip.rs
  - struct_unpacked_array_member.rs
  - submodule_packed_struct_member_contassign.rs
  - tagged_union_matches.rs
  - tagged_union_pattern_literal.rs
  - task_formal_param_width.rs
  - task_fsm_compile.rs
  - tf_port_direction_inheritance.rs
  - type_param_bound_to_specialization.rs
  - type_param_static_property.rs
  - typedef_bits_of_signal_dims.rs
  - typedef_chain_local_namespace.rs
  - typedef_declaring_scope.rs
  - typedef_specialization_dispatch.rs
  - typedef_two_state_and_untyped_param_sign.rs
  - typeparam_default_resolution.rs
  - typeparam_typeid_create.rs
  - typeref_param_static_local.rs
  - unary_context_width.rs
  - union_shared_storage.rs
  - unit_scope_user_type_var.rs
  - unpacked_array_ports_and_vif_arrays.rs
  - unpacked_elem_compare_width.rs
  - unpacked_struct_array_members.rs
  - unpacked_struct_func_arg.rs
  - valparam_spec_cycle.rs
  - value_param_specialization.rs
  - vcd_param_as_wire.rs
  - wide_signed_arith_and_power.rs
  - width_context_discipline.rs
  - wire_typedef_declarations.rs
  - zero_mask_call_elision.rs
  - zero_width_select_confidence.rs
- - uvm_complete_test.sv
  - uvm_ral_backdoor.sv
  - uvm_ral_frontdoor.sv
  - uvm_sequencer_handshake.sv
- classes.rs
- clockgen_x_clock_stays_x.sv
- collections.rs
- fork_wait_deadlock.sv
- gates.rs
- hierarchy.rs
- misc.rs
- perf.rs
- reg3456_pure_sv.sv
- reg4712_visitor_traversal.sv
- scheduling.rs
- strings.rs
- tests
- typename_param_class.sv
- types.rs
- xtrace_kitchen.sv
- xtrace_str3.sv
.gitignore
Cargo.toml
LICENSE
README.md

// repository documentation

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# xezim — SystemVerilog Simulator (Rust)

**xezim** is an **extensible, AI-native SystemVerilog simulator written in Rust** — built so new language features and analyses can be added one verified step at a time, with AI agents as first-class contributors to the codebase.

> `xezim` was previously developed under the name `sisSIM`. The binary, library, and compiled-artifact magic were renamed in place; behavior is unchanged.

This project explores whether modern tools and AI can dramatically reduce the complexity of building core EDA infrastructure such as simulators.

The simulator parses SystemVerilog source code, builds an internal representation, and executes simulations for combinational and sequential logic.

---

# Motivation

Traditional EDA tools require very large engineering teams and many years of development.

This project explores a key question:

> Can a small team — or even a single engineer with AI assistance — build core EDA tools such as a SystemVerilog simulator?

The simulator is being developed incrementally, starting from simple combinational logic and gradually adding more SystemVerilog features.

---

# Features

Current capabilities include:

* IEEE 1800-2023 grammar by default (`--sv2017` opts back to the earlier edition)
* SystemVerilog module parsing
* Signal and net representation
* Continuous assignments
* Basic expression evaluation
* Combinational logic simulation
* Sequential simulation infrastructure
* Test execution framework
* Waveform / trace dumps — VCD (`$dumpfile`/`$dumpvars`; IEEE 1800-2017 §21.7, and
  matches Verilator/Icarus in GTKWave), **FST** (`--fst`, GTKWave's binary format,
  written on a dedicated writer thread with scope filtering), and XTrace v1.0
  (`--xtrace`, optional zstd compression + scope filtering). All three are
  cross-checked against each other by decoding them, not by file size.
* **UVM run-phase execution** (Accellera **1800.2-2017 and 1800.2-2020.3.1**, with
  `-DUVM_NO_DPI`) — a real UVM testbench runs end-to-end: build → connect → topology →
  `run_phase` stimulus → sequencer↔driver TLM handshake → packet collection →
  objection-driven termination → report summary. The reference testbench
  (GettingVerilatorStartedWithUVM) reaches exact Verilator parity on the 2017
  library and runs green on 2020.3.1, and 32/35 UVM 1800.2-2017 example
  testbenches pass. Multiple top
  modules (`-s hdl_top -s hvl_top`) and virtual-interface `config_db` are supported.
  See [docs/uvm-guide.md](docs/uvm-guide.md).
* UVM 1.2 runtime support, also demonstrated by running the `riscv-dv` instruction
  generator end-to-end (random RV32IMC programs that assemble cleanly with
  `riscv64-unknown-elf-as -march=rv32imc_zicsr_zifencei`)
* Event-driven edge gating (`XEZIM_EVENT_EDGE=1`) — opt-in skip of clocked
  flop fires whose data inputs haven't changed; 1.13-1.30× wall on the C910 /
  C906 hello / memcpy / cmark benchmarks, correct-by-construction
* **DPI-C loading** via `--dpi-lib <path>` — load shared libraries of
  `import "DPI-C"` implementations written in C or C++ (e.g. an ISS shim, a
  custom HDL-backdoor force/release layer, or your own UVM extensions). The
  repo ships minimal `svdpi.h` and `vpi_user.h` so DPI code compiles without a
  vendor install. See [docs/dpi-guide.md](docs/dpi-guide.md).
* **Event-control `iff` guards** (LRM §9.4.2.3) — `@(posedge clk iff rst_n)`
  is honored in both procedural `@` waits and edge-sensitive `always` blocks:
  the process resumes only on an edge where the guard holds.
* **User-defined nettypes with resolution functions** (LRM §6.6.7) —
  `nettype T wire_t with resolver;` including Z-skip and built-in resolution.
* **Per-module timescales** (LRM §3.14, §20.3, §21.3.5) — `$time`/`$realtime`
  scale to the calling module's time unit; `timeunit`/`timeprecision`
  declarations scale delays; `$timeformat`/`%t` and `$printtimescale` are
  honored; precision down to `fs`. Modules without a source-level timescale can
  be assigned one from the CLI (see
  [`--module-timescale`](#module-timescale-extension)).
* **VPI loading** via `--vpi-lib <path>` (`-m`) — classic VPI modules run their
  `vlog_startup_routines`: system-task/function registration (`vpi_register_systf`)
  and design iteration (`vpi_iterate`/`vpi_scan`, handle/property access).
* **cocotb** — Python testbenches run against xezim through a runner backend
  (`contrib/cocotb/xezim_runner.py`) on top of the VPI layer, including timed and
  synchronous callbacks.
* **Native compilation** (`--features jit`) — hot bytecode compiles to machine
  code, either through the in-process JIT (`XEZIM_JIT=1`) or the AOT backend
  (`XEZIM_JIT=1 XEZIM_AOT=1`), which emits Rust for eligible combinational
  entries, edge blocks, and process FSMs, builds it with `rustc`, and caches
  the resulting library across runs. See [below](#native-compilation).
* **`bind` by instance path** (§23.11) — `bind top.u_dut.u_sub target_tb u_tb();`
  and the colon form bind only the named instances, with upward references from
  the bound module resolving against the instance they were bound into.

### Non-standard extensions

These are **not** part of IEEE 1800 — they are de-facto vendor (Verilog-XL / VCS /
Questa / Xcelium) extensions supported for compatibility with existing gate-level
and testbench flows. Portable code should not rely on them.

* **`$deposit(target, value)`** — sets `target` to `value` immediately *without*
  installing a persistent driver: the value holds until the next driver
  transaction overwrites it (on an undriven net it simply sticks). This is a
  Verilog-XL/VCS system task, **not** in the LRM. xezim matches the vendor
  semantics — a variable keeps the deposited value, and a real driver on a net
  overrides a deposit on its next update.
* Gate-level-simulation CLI flags — `+nospecify`, `+notimingcheck`,
  `+delay_mode_zero`/`+delay_mode_unit`, `+mindelays`/`+typdelays`/`+maxdelays`,
  and the `-v`/`-y`/`+libext+` library flags — mirror the commercial spellings.

---

# What's new in 0.10

### 0.10.1 – 0.10.3 — native compilation and process conformance (August 2026)

* **AOT native backend** (`XEZIM_JIT=1 XEZIM_AOT=1`, needs a `--features jit` build) — the
  compiler emits Rust for eligible combinational entries, edge blocks, and
  process FSMs, builds it with `rustc`, and loads it through a single exported
  API symbol. On the C910 CoreMark run 18,916 / 21,305 edge blocks and
  108,248 / 215,494 combinational entries compile natively.
* **Persistent native cache** — the generated library is keyed on the source,
  optimization level, and xezim build, then stored under
  `$XEZIM_CACHE_DIR` / `$XDG_CACHE_HOME/xezim/native` / `~/.cache/xezim/native`.
  The first run pays the `rustc` cost; later runs load the cached `.so`
  directly. `XEZIM_NO_NATIVE_CACHE=1` opts out.
* **Compiled process FSMs** (`XEZIM_PROC_FSM=1`) — a blocking `always` body
  compiles into a bytecode state machine with explicit wait instructions, so a
  resume re-enters at the saved program counter with per-process registers
  instead of re-walking the AST continuation chain. Blocking tasks and
  `initial` blocks inline into the same FSM, and the FSMs themselves are
  eligible for the native backend.
* **Blocking task calls inside clocked blocks follow process semantics**
  (§9.2.2) — an `always @(posedge clk)` body that calls a task which consumes
  time is no longer executed on the fast edge path. Previously the callee's
  delay advanced simulation time while that slot's non-blocking updates were
  still queued, so a `q <= d;` scheduled before the call committed a few
  picoseconds late; edges arriving mid-call were also mishandled. Such blocks
  now run as processes: NBAs commit in their own slot, and edges that arrive
  while the body is busy are missed, matching the reference simulator.
* **Delays quantize at the declaring scope's precision** (§3.14.3) — a constant
  fractional delay such as `#0.002` is folded and snapped to the precision grid
  of the scope that declares it, at elaboration time, including delays inside
  interface and class methods.
* **`bind` by instance path** (§23.11) — `bind top.u_dut.u_sub tb u_tb();` and
  the colon form specialize only the named instances; module-name binds are
  applied before path binds, and upward references from the bound module
  resolve against the instance it was bound into.
* **Opt-in combinational region fusion** (`XEZIM_REGIONS=1`) — dependency-
  connected compiled entries fuse into topologically ordered region blocks.
  Measured net-negative on the current benchmark set (recompute cost outweighs
  the dispatch saving), so it ships off by default and stays available for
  experiments.

### 0.10.0 — waveform integrity, cocotb, and class-storage fixes (August 2026)

* **FST dumps are correct at scale** — a break-even compression case wrote the
  time table raw while flagging it compressed, corrupting large dumps in
  GTKWave; the writer now records what it actually wrote, dumps are finalized on
  `Ctrl-C`, the final time slot is flushed, and values render on the writer
  thread instead of the simulation thread. Cross-format agreement is checked by
  decoding VCD, FST, and XTrace, not by comparing file sizes.
* **cocotb backend** — Python testbenches run against xezim via
  `contrib/cocotb/xezim_runner.py`, backed by VPI timed and synchronous
  callbacks and a repaired VPI object model.
* **Scheduling-region fixes** — the postponed region is serviced from the nested
  event loop and on livelock recovery, and a delay closes out the slot it
  resumed in, which removed a `$monitor`-vs-waveform timestamp skew.
* **Class and scope storage** — class member arrays resolve through the runtime
  class, `localparam` arrays inside classes elaborate, each instance gets its
  own static task local under non-blocking assignment, packed-struct formals
  read their members from the call frame, and `%m` no longer leaks the scope of
  a suspended task.

---

# What's new in 0.9

### 0.9.8 — reference-parity audit campaign (August 2026)

Dozens of differential test batteries were run against a commercial reference
simulator; every divergence found was measured construct-by-construct, fixed,
and pinned with a regression test citing the LRM section:

* **Per-evaluator continuous-assign propagation is now the default** (#35) —
  combinational updates propagate with LRM evaluation ordering instead of a
  single batched settle, resolving process-observation orderings that were
  previously unattainable with either batching mode. Escape hatches:
  `XEZIM_EAGER_PROC_SETTLE=1` (previous default) and `XEZIM_LAZY_PROC_SETTLE=1`.
* **UVM `run_test()` termination** (#109) — the phase scheduler advances time
  through run-phase objections; live regression pins run the real Accellera
  library (1.2, 1800.2-2017, 1800.2-2020) in every CI gate.
* **Package export semantics** (§26.6) — `export P::*`, `export P::sym` and
  `export *::*` are honored: a wildcard import re-exposes a package's own
  imports only when exported, and a wildcard export covers only names the
  exporting package references — unexported/unreferenced names are rejected
  exactly as the reference rejects them.
* **Implicitly-static initializer legality** (§6.21) — a local variable with an
  initializer in a static-lifetime task/function is now a compile error
  (explicit `static`/`automatic` required), matching reference behavior;
  for-header declarations, block locals and class methods stay accepted.
* **`alias` as true net unification** (§10.11) and `trireg` charge storage
  (§6.6.4) — aliased nets share one signal slot rather than lowering to an
  assign cycle.
* **Cycle delays synchronize** (§14.11) — `##0` (and a runtime `##(n)` that
  evaluates to 0) waits for the default clocking event when off-edge and is a
  no-op at the edge; `##n` without a designated `default clocking` is rejected.
* **Formatting parity** (§21.2.1.7, §21.2.1.3) — associative arrays print with
  the reference's `'{k:v, ... }` spacing; explicit-width `%h`/`%b`/`%o`
  zero-pad to the minimal core without truncation.
* **Array-method iterators** (§7.12) — `q.sort(x) with (x)` binds the declared
  iterator (sorts and `with`-reductions no longer act on zeros); event controls
  on packed-struct fields (§9.4.2) arm the base vector with a field-value
  compare instead of waking spuriously.
* **`ref` formals alias the actual** (§13.5.2) — callee writes are visible to
  parallel observers mid-call, observer writes reach the callee, and the
  element identity of `ref arr[i]` is frozen at call time.

* **UVM 1800.2-2020.3.1 runs green** — the reference testbench passes against the
  2020.3.1 library (`UVM_ERROR : 0` / `UVM_FATAL : 0`, in/out monitors agree).
  Closing this required a general preprocessor fix (inline
  `` `ifdef ``/`` `endif `` mid-line, §22.6), class-body `localparam` constants,
  and sequencer-path fixes (`process::self()`, fork/join_none automatic-variable
  sharing).
* **User-defined nettypes** (LRM §6.6.7) — `nettype` declarations with
  user resolution functions, Z-skip, and built-in resolution.
* **Per-module timescales** — `$time`/`$realtime` scale to the calling module's
  unit; `timeunit`/`timeprecision` declarations scale delays; `$timeformat`/`%t`
  and `$printtimescale` honored; sub-ns precision down to `fs`; new
  [`--module-timescale`](#module-timescale-extension) CLI extension for
  legacy RTL with no source-level timescale.
* **String & aggregate conformance fixes** — `s[i]` read/write on string
  variables (§11.4.13), `ref`/`output` queue arguments copy back on return
  (§13.5.2), `%p` renders function-local queues/associative arrays (§21.2.1.7),
  `foreach` over a string iterates its content length, `q = {}` clears string
  queues, and a never-touched module-scope queue reports `size() == 0`.
* **Free functions no longer see the caller's class context** (§13.4) — a bare
  name in a package/module function that collided with a caller class property
  used to silently alias the property; queue-property access from outside the
  class (`obj.q.push_back(x)`, `%p` of `obj.q`) now resolves correctly.
* **Gate-level & structural robustness** — multi-dimensional packed arrays of
  unpacked elements (`arr[i][j]`, §7.4), `foreach` over negative/descending and
  packed dimensions (§12.7.3), non-ANSI ports completed by a `reg`/`logic`
  declaration (§23.2.2.1), and per-iteration uniquification of declarations
  inside **nested** generate-for loops (`for(a) for(b) localparam Idx = f(a,b)`).
* **Behavioral clocks & PLLs** — a clock generator whose delay reads a runtime
  variable (`always #(half) clk = ~clk`) now re-evaluates its period every
  toggle, so a PLL reprogrammed at runtime actually changes frequency; verified
  against a commercial simulator alongside UDP primitives, tristate/pull
  strengths, `specify`/timing-check, and divider chains.
* **Dead-clock watchdog** — `XEZIM_STUCK_CLOCK` flags a process parked on a
  clock/reset that never changes while the design keeps churning edges (an
  undriven-net / dropped-cell hang), turning a silent multi-minute grind into an
  immediate, actionable diagnostic (`warn` by default; `abort` for CI).

---

# Project Structure

xezim is split across two repos; this repo depends on `xezim-core` as a **git
dependency** (Cargo clones it automatically — no submodule, no manual checkout):

```
xezim-core (git dep) — shared library: parser, elaboration, value, SDF, VCD sink
./                   — bytecode interpreter + simulator (this repo, binary: xezim)
```

This repo:

```
.
├── src/
│   ├── compiler/
│   │   ├── simulator.rs   — event-driven simulator + bytecode VM
│   │   ├── bytecode.rs    — bytecode compiler for cont_assigns and always blocks
│   │   └── mod.rs         — re-exports value/elaborate/sdf from xezim-core
│   ├── lib.rs             — wraps xezim_core::parse_and_elaborate_multi + Simulator
│   └── main.rs            — CLI entry point (binary: xezim)
├── tests/                 — Rust integration tests + SV compliance suite
├── examples/
└── Cargo.toml             — depends on xezim-core (git dependency, fetched by cargo)
```

### Components

**Parser & elaboration** — live in `xezim-core`; consumed by both `xezim` and `xezim-b`.

**Simulator** — event-driven VM over a bytecode lowering of cont_assigns and always blocks.

---

# Verified Workloads

End-to-end TEST PASSED with bit-identical results vs the workloads' own
golden expectations:

| Design | Test | sim_time / cycles | baseline wall | +O1 wall |
|---|---|---|---|---|
| XuanTie C910 (dual-core) | hello | sim_time 44695 | 95s | **73s** (1.30×) |
| XuanTie C910 | memcpy ×7000 | sim_time 101965 | 216s | **166s** (1.30×) |
| XuanTie C910 | cmark ×1 (`+iterations=1`, INIT_ZERO=1) | 167124 cycles | 87 min | **73 min** (1.19×) |
| XuanTie C906 (single-core) | memcpy ×50 | — | 99s | **88s** (1.13×) |
| XuanTie C906 | cmark ×1 (INIT_ZERO=1) | 295294 cycles | 714s | **587s** (1.22×) |
| riscv-dv (UVM 1.2) | `+num_of_tests=10` random RV32IMC | — | — | 10/10 assemble clean |

Larger runs measured during the 0.10 campaign:

| Design | Test | Result | wall |
|---|---|---|---|
| lowRISC Ibex (`simple_system`) | CoreMark ×10 | score 2.477304 CoreMark/MHz, 2,765,321 instret, halt at 41,454,505 ns — byte-identical | 447s |
| XuanTie C906 | cmark ×2 | TEST PASSED, 286,469 cycles/iteration | 516s |
| XuanTie C910 (dual-core) | cmark ×2 | TEST PASSED, CoreMark 6.327752, halt at 34,985,250 | 8,028s, including a cold native compile of the whole design |
| mbits-mirafra AVIP suite (UVM) | apb / spi / i3c / axi4 / axi4Lite base tests | 5 of 5 reproduce the reference's `UVM_ERROR` counts and end times exactly; `ahb` runs in xezim but the reference fails to elaborate it, and `uart` is a known open stall | 33s for axi4Lite (28s with FSM + AOT), seconds for the rest |

On these CPU workloads a commercial reference simulator is still roughly
4–5× faster; the campaign narrowed the Ibex CoreMark gap from about 30× to
4.3×. The remaining cost is evaluation, not scheduling.

UVM run-phase (see [docs/uvm-guide.md](docs/uvm-guide.md)):

| Testbench | Result |
|---|---|
| GettingVerilatorStartedWithUVM vs **1800.2-2017** (`data0`/`data1`/`random`/`many_random`) | 4/4 — exact Verilator parity (monitors agree, `UVM_ERROR`/`UVM_FATAL` = 0) |
| GettingVerilatorStartedWithUVM vs **1800.2-2020.3.1** | green — in/out monitors agree (77/77 packets), `UVM_ERROR`/`UVM_FATAL` = 0 |
| sv-tests UVM 1800.2-2017 example suite | 32/35 pass (3 out of scope: deprecated UVM-1.0 macros, DPI backdoor) |

---

# Compliance

Full [sv-tests](https://github.com/chipsalliance/sv-tests) run with the
suite's own `xezim` runner (`make report RUNNERS=Xezim`), xezim 0.8.1. The
generated HTML report and per-test CSV are checked in under `reports/`
(`svtests_index.html`, `svtests_report.csv`, and `sv-tests-compliance.md`).

| Category | Pass / Total | Rate |
|---|---|---|
| **All tests** | **4354 / 4768** | **91.3 %** |
| &nbsp;&nbsp;UVM (1800.2-2017) | 484 / 487 | 99.4 % |
| &nbsp;&nbsp;non-`ivtest` | 2153 / 2237 | 96.2 % |
| &nbsp;&nbsp;Icarus `ivtest` suite | 2201 / 2531 | 87.0 % |

An earlier run scored only 52 % because a `-I` library directory
(`ivtest/ivltests/`, ~1000 mutually independent single-file tests) was scanned
too eagerly: xezim honors IEEE §23.3.2 library semantics — an `-I` dir supplies
module definitions to satisfy unresolved instantiations — but it was adopting
*every* definition in the directory, so typedefs/enums from unrelated sibling
files leaked into the primary design and failed a spurious §6.18 base-type
check. `resolve_library_modules` now pulls in only the library modules actually
reachable from the compiled design (transitively), which reclaimed ~1870
`ivtest` cases with no change to the native LRM/UVM results.

---

# Test Suite

~2,200 integration tests run in CI, each in **both** execution modes — the
bytecode interpreter (`cargo test`) and the JIT (`cargo test --features jit`).
A large share are differential tests whose expected values were measured on a
commercial reference simulator; their doc comments cite the LRM section and
the measured behavior.

**Credit:**
All `pr*.v` tests were taken from the **Icarus Verilog test suite**.

These tests help verify correctness against real-world Verilog/SystemVerilog edge cases.

### UVM tests

The UVM integration tests (`tests/classes/uvm_integration_tests.rs`) run against
the real Accellera UVM library from https://github.com/nitronis/UVM — one repo
carrying the 1.1d, 1.2, 1800.2-2017 and 1800.2-2020 releases as subdirectories.
No manual setup is needed: `cargo build` clones it into `target/uvm-checkout`
when no checkout is found (and the tests clone on demand as a fallback). To use
an existing checkout instead, set `XEZIM_UVM_DIR` to its root or clone it as a
`../UVM` sibling of this repo.

---

# Build

Install Rust: https://www.rust-lang.org/tools/install

**If you only want to use xezim, there is nothing else to clone** — `xezim-core`
is a git dependency, and `cargo build` pulls it automatically:

```bash
git clone git@github.com:<you>/xezim.git
cd xezim
cargo build            # debug
cargo build --release  # optimized (recommended for large designs)
```

The release binary is produced at `target/release/xezim`.

### Modifying xezim-core

`xezim-core` (parser + elaboration) is a separate repo, consumed as a git
dependency **pinned to the exact revision this xezim revision was tested
against** (see `rev = ...` in `Cargo.toml`). A bare clone therefore always
builds the verified pair — never an untested newer core — and a release tag
of xezim pairs with the core revision it shipped with. The pin is bumped in
the same commit that starts depending on new core behavior.

**Working on core?** Clone it next to (or inside) this repo and switch the
build to it — after this, plain `cargo build` uses your checkout directly,
with **no network fetch**:

```bash
git clone git@github.com:aionhw/xezim-core.git ../xezim-core
./scripts/use-local-core.sh        # detects ./xezim-core or ../xezim-core
cargo build --release              # builds against the local checkout
```

The script writes a git-ignored `.cargo/config.toml` with a `[patch]` that
overrides the pinned dependency; `./scripts/use-local-core.sh --remove`
returns to the pin. For a one-off invocation without persistent state,
`./scripts/cargo-local.sh build --release` applies the same patch for a
single command when `../xezim-core` exists.

`cargo tree -p xezim-core` shows which copy is in use (a path in parentheses
means your local checkout is active).

**Bumping the pin** (after pushing core): from this repo,

```bash
git -C ../xezim-core rev-parse origin/main   # the freshly pushed rev
# edit both rev = "..." fields in Cargo.toml to that hash, commit, push
```

CI builds the bare-clone path on every push, so a mismatched pin fails
loudly instead of producing a subtly incompatible binary.

---

# Run

Run a simple example via cargo:

```bash
cargo run --release -- examples/test.sv
```

Or invoke the binary directly:

```bash
./target/release/xezim <source_files> [+plusargs] [options]
```

Common options:

| Option | Purpose |
|---|---|
| `-D<MACRO>[=val]` | Define a preprocessor macro |
| `-I<dir>` | Add an include directory |
| `--simulate` | Run the simulation (vs `--parse` / `--compile` / `--preprocess`) |
| `-s <module>` | Select a top-level module. Repeat for multiple roots (e.g. `-s hdl_top -s hvl_top`); xezim elaborates them all under a synthetic wrapper |
| `--dpi-lib <path>` | Load a DPI-C shared library (`.so`/`.dylib`/`.dll`). Repeatable. See [docs/dpi-guide.md](docs/dpi-guide.md). |
| `--vpi-lib <path>` (`-m`) | Load a VPI module and run its `vlog_startup_routines` (system-task registration, design walk). Repeatable. |
| `--module-timescale [mods=]<unit>/<prec>` | Assign a timescale to modules with no explicit source-level one. See [below](#module-timescale-extension). Repeatable. |
| `--dump-timescales` | Print every module's resolved timescale before the run (no source `$printtimescale` needed); modules with no `` `timescale `` are flagged. See [below](#module-timescale-extension). |
| `--max-time <N>[ps\|ns\|us\|ms\|s]` | Stop simulation after `N` of simulated time — **nanoseconds** when no unit is given. The cap is resolved to whole nanoseconds (a sub-ns value rounds to the nearest one; below half a nanosecond is rejected) and then converted to the design's tick, so the same `--max-time` covers the same simulated time whatever the precision |
| `+trace`, `+<plusarg>` | Passed through to `$value$plusargs` / `$test$plusargs` |
| `+seed=<n>` | Seed the RNG for a reproducible run (same seed ⇒ byte-identical output; affects e.g. the number of packets a random UVM test collects) |
| `--sdf <file>` `--sdf-{min,typ,max}` | Annotate standard delays |
| `--sim-debug` | Print `[DEBUG]` / `[OPT]` diagnostics (`--sim_debug` still accepted) |
| `--verbose` | Per-file compile progress: each file as it is parsed, and the modules/blocks it contributed to the working library |
| `--dump-files-list` | Print the fully resolved file list after `-f` expansion, then exit — confirms *which* sources a build actually reads |
| `--dump-merged-sv <file>` | Write the sources as one preprocessed, self-contained `.sv`. With `-s <top>`, keeps only the files that top needs. See [below](#reducing-a-multi-file-build) |
| `--artifact-compression <none\|1-22>` | Compression level for the `-o` compiled artifact (`none` writes it raw) |
| `--cache-dir <dir>` | Select the automatic elaborated-design cache directory |
| `--no-cache` | Disable the automatic elaborated-design cache |
| `-l`, `--log <file>` | Redirect all stdout/stderr — including DPI/VPI C output — to a log file |
| `-v <file>` | Library file: modules compiled only to resolve unresolved instantiations |
| `-y <dir>` | Library directory: `<module>.<ext>` loaded on demand |
| `+libext+<ext>+…` | Extension list for `-y` search (replaces the default `.v`/`.sv`/`.V`) |
| `+nospecify` | Suppress specify-block path delays — zero-delay gate simulation (`-nospecify` also accepted) |
| `+notimingcheck` | Accepted no-op: specify timing checks are not modeled (also `+notimingchecks`/`-notimingchecks`) |
| `--fst <file>` | Emit an FST (GTKWave binary) waveform dump |
| `--fst-scope <hier>` | Restrict the FST dump to signals under `<hier>` (repeatable) |
| `--xtrace <file>` | Emit an XTrace v1.0 dump (`.zst`/`.zstd` ⇒ zstd-compressed) |
| `--xtrace-scope <hier>` | Restrict the XTrace dump to signals under `<hier>` (repeatable) |
| `--relax-implicit-static` | Accept `int x = ...;` inside a static task/function (§6.21) with a warning instead of an error — for vendor sources you cannot edit |
| `--error-exit` | Exit nonzero if any `$error` was reported (`$fatal` always does) |

Selected env knobs (off by default unless noted):

| Env var | Effect |
|---|---|
| `XEZIM_EVENT_EDGE=1` | Skip gateable clocked flop fires whose data is unchanged (1.13-1.30× wall on c910/c906) |
| `XEZIM_JIT=1` | Compile bytecode blocks to machine code in-process (needs a `--features jit` build) |
| `XEZIM_AOT=1` | Compile eligible blocks to native code via generated Rust + `rustc` instead of cranelift. **Requires `XEZIM_JIT=1` as well** — on its own it is a no-op. Needs `--features jit`. See [below](#native-compilation) |
| `XEZIM_AOT_OPT=0..3` | `rustc` optimization level for the generated crate (default 2) |
| `XEZIM_PROC_FSM=1` | Compile blocking `always` bodies into bytecode state machines with wait instructions |
| `XEZIM_NO_NATIVE_CACHE=1` | Disable the persistent native-library cache (`~/.cache/xezim/native`) |
| `XEZIM_REGIONS=1` | Fuse dependency-connected compiled combinational entries into region blocks (experimental; currently net-negative on the benchmark set) |
| `XEZIM_STUCK_CLOCK=1` | Flag a process parked on a clock/reset that never changes while the design keeps churning edges (`abort` variant for CI) |
| `XEZIM_INIT_ZERO=1` | Coerce X-initialized signals/arrays to 0 (required for some C910/C906 workloads, e.g. cmark) |
| `XEZIM_PROGRESS=N` | Emit a `[PROGRESS]` line every N wall-seconds (sim_time, iters, edges_fired, nba_q) |
| `XEZIM_CACHE_DIR=<dir>` | Override the elaborated-design cache directory |
| `XEZIM_NO_CACHE=1` | Disable the automatic elaborated-design cache |
| `XEZIM_COMPILE_PHASES=1` | Report detailed simulator compilation phase timings |
| `XEZIM_ALLOW_IMPLICIT_STATIC=1` | Same as `--relax-implicit-static` |
| `XEZIM_MAX_INST_DEPTH=N` | Instantiation-depth cap (default 200) — turns unbounded recursive instantiation into a clean error instead of memory exhaustion |
| `XEZIM_STACK_MB=N` | Stack size of the simulation worker thread (default 1024; `0` runs on the main thread) |
| `XEZIM_VALUE_TRACE=<substr>[,...]` | Print every committed change of signals whose hierarchical name contains a pattern: time, name, old→new value, dispatch phase, writing process origin (file:line). NBA commits are labeled `nba` |
| `XEZIM_VALUE_TRACE_LIMIT=N` | Cap value-trace output lines (default 20000) |

Example — run the picorv32 testbench against a gate-level netlist:

```bash
./target/release/xezim testbench.v synth.v \
    +firmware=firmware/firmware.hex --max-time 50000000
```

## Native compilation

Built with `--features jit`, xezim can turn hot bytecode into machine code.

```bash
cargo build --release --features jit

# in-process JIT
XEZIM_JIT=1 ./target/release/xezim <sources> -s <top>

# AOT: generate Rust, build it with rustc, load the result
# (XEZIM_JIT=1 is required — XEZIM_AOT selects the backend, it does not
#  enable native compilation on its own)
XEZIM_JIT=1 XEZIM_AOT=1 ./target/release/xezim <sources> -s <top>

# AOT plus compiled process state machines
XEZIM_JIT=1 XEZIM_AOT=1 XEZIM_PROC_FSM=1 ./target/release/xezim <sources> -s <top>
```

The AOT backend covers combinational entries, edge-sensitive blocks, and — when
`XEZIM_PROC_FSM=1` is also set — process FSMs. Blocks it cannot lower (values
wider than 64 bits, unsupported opcodes, X/Z-carrying shapes) stay on the
interpreter, so coverage is partial by design; `XEZIM_JIT_VERBOSE=1` prints the
`[AOT] … compiled N/M` summary.

Generating and compiling that Rust is the dominant cost on a first run — minutes
on a large SoC — so the resulting library is cached under `$XEZIM_CACHE_DIR`,
`$XDG_CACHE_HOME/xezim/native`, or `~/.cache/xezim/native`, keyed on the
generated source, `XEZIM_AOT_OPT`, and the xezim build. Repeat runs load the
cached `.so` directly. Set `XEZIM_NO_NATIVE_CACHE=1` to force a rebuild, and
`XEZIM_AOT_OPT=0` to trade steady-state speed for a faster build.

## Warm design cache

Simulation mode stores a content-addressed elaborated design and compiled
combinational worklist after the first run, then reuses both on identical later
runs. A cache hit skips parsing, elaboration, and combinational dependency-index
construction, while simulator state, plusargs, time-zero initialization, and
event scheduling are rebuilt for every invocation. Timing-annotated and UDP
designs conservatively rebuild the worklist. The key covers source and library
contents, defines, include paths, top selection, language/strictness, timescale
and delay settings, and the xezim executable build.

The default directory is `$XEZIM_CACHE_DIR`, then
`$XDG_CACHE_HOME/xezim/designs`, then `$HOME/.cache/xezim/designs`. Use
`--cache-dir` for a workload-local cache or `--no-cache` for a cold run. Xezim
prints `[CACHE] miss`, `[CACHE] stored`, or `[CACHE] hit` on stderr.

## Reducing a multi-file build

Three flags answer the questions that come up when a large `-f` build does not
behave: *which* files were read, *what* each contributed, and *what does the
code look like after preprocessing*.

```bash
xezim -f build.args --dump-files-list          # the resolved file list, then exit
xezim -f build.args -s testbench --verbose     # each file as it is parsed, and what it defined
xezim --parse -f build.args -s testbench --dump-merged-sv repro.sv
```

`--dump-merged-sv` writes every source into one self-contained `.sv` with
`` `ifdef `` branches resolved, macros expanded and `` `include ``s inlined — a
125-file build becomes a single re-runnable file. Given `-s <top>` it keeps only
the files that top actually needs, which is what makes the result small enough
to hand to someone else.

Two properties are worth knowing before relying on it:

* **The reduction is per file, not per module.** A file defining both a module
  you need and one you do not drags the second one's dependencies in too.
* **The closure is lexical and runs before parsing**, so the dump still works on
  a design that does not elaborate — the case the flag exists for. It is
  conservative in the safe direction: it may keep a file more than strictly
  needed, never one fewer. Files that declare no design unit at all (a
  file-scope `typedef`/function, a top-level `bind`) are always kept, since
  nothing references them by name and dropping them would change behaviour.

Note `--parse` above: the dump is produced before elaboration, so a design whose
elaboration takes minutes still dumps in seconds. Only the step that appends
adopted `-v`/`-y` library files needs `--compile` or `--simulate`.

## Module-timescale extension

`--module-timescale` is an xezim-specific command-line extension. It assigns a
time unit and precision to module *definitions* that have **no explicit
source-level timescale**, without changing the semantics of the source. It is
handy for retrofitting a timescale onto legacy RTL that omits one, or onto a
mix of files where only some carry `` `timescale ``.

```bash
# Every module without an explicit timescale gets 1ns/1ps:
xezim --module-timescale 1ns/1ps design.sv

# Only the listed definitions (comma-separated), 10ns/1ns:
xezim --module-timescale cpu,cache=10ns/1ns design.sv

# Repeatable; the named form wins over the global one:
xezim --module-timescale 1ns/1ps --module-timescale mem_ctrl=1ps/1fs design.sv
```

**A module has an explicit source-level timescale** — which the option never
overrides — when it has a `timeunit`/`timeprecision` declaration, **or** a
`` `timescale `` directive is active where it is declared (`` `resetall ``
clears that). Effective precedence, highest first:

1. module-local `timeunit` / `timeprecision`
2. an active `` `timescale `` directive
3. a named `--module-timescale mods=<unit>/<prec>`
4. a global `--module-timescale <unit>/<prec>`
5. the 1ns / 1ns default

The precision must be equal to or finer than the unit (`1ns/1ps` is legal,
`1ps/1ns` is an error). Two *different* named assignments for the same module
are an error; an unmatched name, or one that lands on a module that already has
an explicit timescale, is a warning (the assignment is ignored). Assignments
apply to a definition, so every instance of it shares the timescale.

Sub-nanosecond precision is honoured — the simulation tick is the finest
precision declared anywhere in the design, down to `fs`. `--max-time` is
independent of that: it is given in nanoseconds and converted to the tick, so
`--max-time 100` stops at 100 ns whether the design runs at `1ns` or `1fs`
precision. What a finer precision does change is the *number of ticks* covered,
and hence the wall-clock cost of reaching the same simulated time. Reported
times (`$time`, the closing `Simulation finished at time …`) are in ticks, so
the same run prints `100` at `1ns/1ns` and `100000` at `1ns/1ps`.

Because the cap is held in whole nanoseconds, a sub-nanosecond `--max-time`
(`--max-time 1ps`) is rejected rather than silently rounded to zero. To stop a
run as early as possible, prefer `--parse` or `--compile`, which never start a
simulation at all.

### Inspecting resolved timescales

`--dump-timescales` prints the resolved timescale of every module *before* the
run — no source `$printtimescale` calls required. It reports each definition's
`` `timescale `` semantics (an explicit/`--module-timescale` value, or the
`1s/1s` default when a module has none) and flags the modules that carry no
`` `timescale ``. Combine it with `--module-timescale` to confirm an assignment
landed where you intended.

```bash
$ xezim --dump-timescales design.sv
=== module timescales (3 modules) ===
  cache                        10ns / 1ns
  cpu                          1ns / 1ps
  glue                         1s / 1s   (no `timescale — 1s/1s default)
======================================
```

A flagged module also emits the `has no timescale directive` warning in a
mixed-timescale design; give it a source `` `timescale `` or a
`--module-timescale` assignment to resolve it. (The reported `1s/1s` is the
IEEE-default *display* value; such a module's effective delay unit is the
design's global tick — a further reason to declare one explicitly.)

---

# Development Workflow

Typical development loop:

```
edit code
↓
cargo build
↓
run tests
↓
add new SystemVerilog features
```

Rust provides strong guarantees for memory safety and concurrency, making it well suited for building large-scale EDA infrastructure.

---

# Long-Term Vision

This project explores several long-term ideas:

* **AI-assisted EDA development**
* **Rapid simulator prototyping**
* **Cloud-scale simulation**
* **Distributed multi-CPU simulation**

The goal is to investigate whether modern software and AI tools can dramatically accelerate the creation of chip design infrastructure.

---

# License

Apache License 2.0

See the `LICENSE` file for details.

---

# Contributors

xezim is developed in the open, and a number of people have improved it through
pull requests. Thank you to everyone who has contributed — bug fixes, features,
tests, and tooling all move the project forward:

* **Thomas Burg** — class-system and UVM fixes: static-property chains through
  object handles (§8.25), associative-array method dispatch and ref-writeback,
  `ClassName::static_prop` access, parser-gap self-tests, and test-harness
  hardening.
* **Oscar Gustafsson** — expanded VPI functionality (`vpi_get_value`,
  `ObjectValType`), CI setup, and clippy cleanups.
* **Chen Ben Haroosh** — submodule-inline generate-for elaboration: genvar-
  dependent declarations and `parameter type` default resolution, plus the
  accompanying SystemVerilog compliance cases.
* **Jayaraman RP** — cross-platform installation scripts, including the macOS
  installer with UVM setup.

New contributors are welcome — see [Development Workflow](#development-workflow).

---

# Acknowledgements

* Icarus Verilog project for the public test suite
* The Rust community
* Open-source EDA projects

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