DESIGN-BASIC-LOGIC-GATES-USING-VERILOG-
Objective-To design and simulate basic logic gates (AND,OR,NOT,XOR)using Verilog HDL and verify their functionality by simulating using ModelSim. AND Gate:output is 1 when all inputs are 1. OR Gate- Output is 1 when atleast one input is 1 . NOT Gate-Inverts the input. XOR Gate : Output is 1 when inputs are different
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