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the awesome work, project and lab of EDA (Electronic Design Automation). continue update...

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# EDA-info
the awesome work, project and lab of EDA (Electronic Design Automation). continue update...
(Because of personal reasons, we will not continue update...)

- Main EDA lab and open-source project：
  - [Bei Yu, The Chinese University of Hong Kong](http://www.cse.cuhk.edu.hk/~byu/)
  - [Evangeline F.Y. Young, The Chinese University of Hong Kong](https://www.cse.cuhk.edu.hk/~fyyoung/)
  - [Yibo Lin, The Peking Unbiversity](https://yibolin.com/)
  - [The UT Design Automation Laboratory (UTDA)](https://www.cerc.utexas.edu/utda/)
  - [iEDA](https://github.com/OSCC-Project/iEDA)
  - [Xuan Zeng, The Fudan Unbiversity](https://ieeexplore.ieee.org/author/37272246100?history=no&highlight=true&returnType=SEARCH&sortType=newest&searchWithin=%22Author%20Ids%22:37272246100&returnFacets=ALL)

- Overview:
  - [Machine learning and algorithms: Let us team up for EDA](https://ieeexplore.ieee.org/abstract/document/9682429/)
- Placement and Routing
	- Routing: 
		- [FastRoute](https://github.com/The-OpenROAD-Project-Attic/FastRoute)
    		    : A Step to Integrate Global Routing into Placement
		- [NTHU](https://github.com/luckyrantanplan/nthu-route)
    		    : A New Global Router for Modern Designs
		- [SAGERoute](https://github.com/PKU-IDEA/SAGERoute/tree/main)
    		    : Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility
		- [Dr.CU](https://github.com/cuhk-eda/dr-cu)
       		    : Dr. CU is a VLSI detailed routing tool
		- [Dr.GR](https://github.com/cuhk-eda/cu-gr)
    		    : Dr. CU is a VLSI global routing tool
		- [Align](https://github.com/ALIGN-analoglayout/AnalogDetailedRouter)
    		    : analog detailed router
		- [Electromigration- and Parasitic-Aware ILP-Based Analog Router](https://ieeexplore.ieee.org/abstract/document/8378047/)
    		    : analog global router
		- [Efficient ILP-Based Variant-Grid Analog Router](https://ieeexplore.ieee.org/abstract/document/7527478/)
    		    : analog global router
		- Reinforcement Learning Guided Detailed Routing for Custom Circuits
		- [Pathfinding Model and Lagrangian-Based Global Routing](https://doi.org/10.1109/DAC56929.2023.10247969)
		- [PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning](https://doi.org/10.1109/TCAD.2022.3168259)
		- [GAMER: GPU-Accelerated Maze Routing](https://doi.org/10.1109/TCAD.2022.3184281)
		- [COALA: Concurrently Assigning Wire Segments to Layers for 2-D Global Routing](https://doi.org/10.1109/TCAD.2022.3178353)
		- [Incremental 3-D Global Routing Considering Cell Movement and Complex Routing Constraints](https://doi.org/10.1109/TCAD.2022.3210493)
	- placement:
		- [Xplace](https://github.com/cuhk-eda/Xplace)
    		    : An Extremely Fast and Extensible Global Placement Framework
		- [RePlace](https://github.com/The-OpenROAD-Project/RePlAce)
     		    : Advancing Solution Quality and Routability Validation in Global Placement
		- [DreamPlace](https://github.com/limbo018/DREAMPlace)
    		    : Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement
		- [ePlace](https://github.com/ApeachM/ePlacePractice)
    		    : Electrostatics based Placement using Fast Fourier Transform and Nesterov’s Method
		- [MacroPlacement](https://github.com/TILOS-AI-Institute/MacroPlacement)
    		    : Assessment of Reinforcement Learning for Macro Placement
		- [MaskPlace](https://github.com/laiyao1/maskplace)
  		    : Fast Chip Placement via Reinforced Visual Representation Learning
		- [RLPlace: Deep RL Guided Heuristics for Detailed Placement Optimization](https://doi.org/10.23919/DATE54114.2022.9774684)
		- [Parallel Global Placement on CPU via Parallel Reduction](https://ieeexplore.ieee.org/document/8983444/)
	- analog layout generation
		- [Laygo](https://laygo2.github.io/)
    		    : A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies
		- [BAG](https://github.com/sdaudlin/BAG_framework)
    		    : A Process-Portable Framework for Generator-based AMS Circuit Design
		- [MAGICAL](https://github.com/magical-eda/MAGICAL)
    		    : Machine Generated Analog IC Layout
		- [ALIGN](https://github.com/ALIGN-analoglayout/ALIGN-public)
    		    : Analog Layout, Intelligently Generated from Netlists
		- [Symmetry Annotation Extraction](https://doi.org/10.1145/3394885.3431545)
    		    : Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks
		- [Interactive Analog Layout Editing With Instant Placement and Routing Legalization](https://ieeexplore.ieee.org/document/9826897)

- Analog Circuit Design Optimization
	- [Multi-objective Bayesian Optimization for Analog/RF Circuit Synthesis](https://dl.acm.org/doi/abs/10.1145/3195970.3196078)
	- [Automated Design of Analog Circuits Using Reinforcement Learning](https://ieeexplore.ieee.org/abstract/document/9576505)
   		- [code](https://github.com/ksettaluri6/AutoCkt)
	- [DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks](https://ieeexplore.ieee.org/abstract/document/9586139)
	- [MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-Actors](https://ieeexplore.ieee.org/abstract/document/10136894)
	- [DC-Model: A New Method for Assisting the Analog Circuit Optimization](https://ieeexplore.ieee.org/abstract/document/10129366)
   	- [An efficient batch-constrained bayesian optimization approach for analog circuit synthesis via multiobjective acquisition ensemble](https://ieeexplore.ieee.org/abstract/document/9336041)
   	- [Batch Bayesian optimization via multi-objective acquisition ensemble for automated analog circuit design](http://proceedings.mlr.press/v80/lyu18a.html?ref=https://githubhelp.com)
   	  	- [code](https://github.com/Alaya-in-Matrix/MACE)
   	- [Geometric programming for circuit optimization](https://dl.acm.org/doi/abs/10.1145/1055137.1055148)
   	- [A tutorial on geometric programming](https://link.springer.com/article/10.1007/s11081-007-9001-7)
   	- [Late Breaking Results: Analog Circuit Generator based on Deep Neural Network enhanced Combinatorial Optimization](https://dl.acm.org/doi/abs/10.1145/3316781.3322468)
   	- [Learning to Design Circuits](https://arxiv.org/abs/1812.02734)
   	- [GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning](https://ieeexplore.ieee.org/abstract/document/9218757/)
   	- [Closing the Design Loop: Bayesian Optimization AssistedHierarchical Analog Layout Synthesis](https://ieeexplore.ieee.org/abstract/document/9218621/)
   	- [Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization](https://ieeexplore.ieee.org/abstract/document/9474253)
   	- [Joint optimization of sizing and layout for AMS designs: Challenges and opportunities](https://dl.acm.org/doi/abs/10.1145/3569052.3578929)
   	- [Analog circuit sizing based on Evolutionary Algorithms and deep learning](https://www.sciencedirect.com/science/article/pii/S0957417423019826)
   	- [Reinforcement Learning-based Analog Circuit Optimizer using gm/ID for Sizing](https://ieeexplore.ieee.org/document/10247739)
   	- [Automated Design of Complex Analog Circuits with Multiagent based Reinforcement Learning](https://ieeexplore.ieee.org/document/10247909)
   	- [Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards](https://dl.acm.org/doi/10.1145/3551901.3556474)
  		- [code](https://github.com/electronics-and-drives/MLCAD22)
   	- [LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces](https://dl.acm.org/doi/10.1145/3551901.3556496)
   	- [RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL](https://dl.acm.org/doi/10.1145/3551901.3556487)
   	- [Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits](https://ieeexplore.ieee.org/document/9045614)
   	- [Bayesian optimization approach for analog circuit synthesis using neural network](https://ieeexplore.ieee.org/abstract/document/8714788)
   	- [A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench](https://ieeexplore.ieee.org/document/9712590/)
   	- [High-Dimensional Bayesian Optimization for Automated Analog Circuit Design via Add-Graph Structure](https://ieeexplore.ieee.org/document/9620425)
   	- [A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization](https://ieeexplore.ieee.org/document/9371542)
   	- [An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis](https://ieeexplore.ieee.org/document/9218592)
   	- [A Mixed-Variable Bayesian Optimization Approach for Analog Circuit Synthesis](https://ieeexplore.ieee.org/document/9181162)
   	- [APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors using DNN Learning](https://dl.acm.org/doi/abs/10.1145/3566097.3567880)

- Layout Pattern Generation
  	- [DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder](https://dl.acm.org/doi/abs/10.1145/3316781.3317795)
  	- [Layout Pattern Generation and Legalization with Generative Learning Models](https://dl.acm.org/doi/abs/10.1145/3400302.3415607)
  	- [LayouTransformer: Generating Layout Patterns with Transformer via Sequential Pattern Modeling](https://dl.acm.org/doi/abs/10.1145/3508352.3549350)
  	- [DiffPattern : Layout Pattern Generation via Discrete Diffusion](https://arxiv.org/abs/2303.13060)
  	- [WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout](https://dl.acm.org/doi/10.1145/3316781.3317930)

- Pattern Layout Hotspot Dectection
  	- [Efficient Hotspot Detection via Graph Neural Network](https://ieeexplore.ieee.org/document/9774579)
  	- [Efficient Layout Hotspot Detection via Neural Architecture Search](https://dl.acm.org/doi/10.1145/3517130)
  	- [Hotspot Detection via Attention-Based Deep Layout Metric Learning](https://doi.org/10.1145/3517130)
  	- [Faster Region-based Hotspot Detection](https://doi.org/10.1145/3316781.3317824)
  	  	- [code](https://github.com/Lanselott/R-HSD)
  	- [Efficient Layout Hotspot Detection via Binarized Residual Neural Network](https://doi.org/10.1145/3316781.3317811)
  	- [Hotspot Detection using Squish-Net](https://doi.org/10.1117/12.2515172)
  	- [Detecting multi-layer layout hotspots with adaptive squish patterns](https://dl.acm.org/doi/10.1145/3287624.3288747)
  	- [Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning](https://ieeexplore.ieee.org/document/8360060/)
  	  	- [code](https://github.com/phdyang007/dlhsd)
  	- [Lithography Hotspot Detection: From Shallow To Deep Learning](https://doi.org/10.1109/SOCC.2017.8226047)
  	- [Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning](https://dl.acm.org/doi/10.1145/3061639.3062270)
  	- [Bilinear Lithography Hotspot Detection](https://dl.acm.org/doi/10.1145/3036669.3036673)
  	- [ADAPT: An Adaptive Machine Learning Framework with Application to Lithography Hotspot Detection](https://ieeexplore.ieee.org/abstract/document/9531210/)
  	- [Many-Layer Hotspot Detection by Layer-Attentioned Visual Question Answering](https://doi.org/10.23919/DATE54114.2022.9774622)
  	- [Efficient Layout Hotspot Detection via Binarized Residual Neural Network](https://ieeexplore.ieee.org/document/8806978/)

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