108-RTL-Projects

(★ 63)

Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simple digital circuits to complex system designs. , you'll find valuable resources here to enhance your hardware design skills.

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- weinberger_based_adder.pdf
- Project 100 _ Pipeline Hazard Detector.pdf
- Project 101 Car Wash Controller.pdf
- Project 102_ Password Authentication FSM.pdf
- PROJECT 103_ DIGITAL CLOCK FSM.pdf
- TRAFFIC SIGNAL TIMER .pdf
- Uart Protocol.pdf
- Project_106__Bus_Arbiter_FSM.pdf
- Project_107__Rotating_LED_Display_Controller.pdf
- - Processor_1.xpr
- - project_2.xpr
- - control_tb.sv
  - processor_tb1.sv
  - tb_alu_64bit.sv
  - tb_datapath.sv
  - tb_processor_top.sv
  - tb_register_file_64bit.sv
  - tb_riscv_processor.sv
  - testbench.sv
- 64bitalu_result.png
- 64bitalu_sch.png
- 64bitalu_sys.png
- data_memory_result.png
- data_memorysyn.png
- image (1).png
- image.png
- instruction_memory_result.png
- instruction_memory_sch.png
- instruction_memory_syn.png
- instructiondecode_result.png
- instructiondecode_sny.png
- Source Codes.zip
- 11 LADNER FISCHER ADDER.pdf
- PROJECT_ 12 LING ADDER.pdf
- Project 13_ Serial Adder .pdf
- Project 14_ Wallace Tree Adder.pdf
- 15 DADDA TREE ADDER.pdf
- Project 16_ Conditional Sum Adder.pdf
- 17 Multi-Operand Adder.pdf
- Project 18_ Logarithmic Adder.pdf
- 19 CARRY BYPASS ADDER.pdf
- - clock_divider_sch.png
  - clock_divider_sim.png
  - counter_4bit_sch.png
  - counter_4bit_sim.png
  - d_flip_flop_sch.png
  - d_flip_flop_sim.png
  - decoder_3to8_sch.png
  - decoder_3to8_sim.png
  - encoder_8_to_3_sch.png
  - encoder_8_to_3_sim.png
  - full_adder_sch.png
  - full_adder_sim.png
  - full_subtractor_sch.png
  - full_subtractor_sim.png
  - half_adder_sch.png
  - half_adder_sim.png
  - half_subtractor_sch.png
  - half_subtractor_sim.png
  - jk_flip_flop_sch.png
  - jk_flip_flop_sim.png
  - logic_gates_NAND_sch.png
  - logic_gates_NAND_sim.png
  - logic_gates_sch.png
  - logic_gates_sim.png
  - master_slave_jk_flip_flop_sch.png
  - master_slave_jk_flip_flop_sim.png
  - multiplexer_4to1_sch.png
  - multiplexer_4to1_sim.png
  - sr_flip_flop_sch.png
  - sr_flip_flop_sim.png
  - t_flip_flop_sch.png
  - t_flip_flop_sim.png
- - basic_gates.sv
  - clock_divider.sv
  - clock_divider_tb.sv
  - counter_4bit.sv
  - counter_4bit_tb.sv
  - d_flip_flop.sv
  - d_flip_flop1.sv
  - d_flip_flop1_tb.sv
  - d_flip_flop_tb.sv
  - decoder_3to8.sv
  - decoder_3to8.vh
  - decoder_3to8_tb.sv
  - encoder_8_to_3.sv
  - encoder_8_to_3_tb.sv
  - full_adder.sv
  - full_adder_tb.sv
  - full_subtractor.sv
  - full_subtractor_tb.sv
  - half_adder.sv
  - half_adder_tb.sv
  - half_subtractor.sv
  - half_subtractor_tb.sv
  - jk_flip_flop.sv
  - jk_flip_flop_tb.sv
  - logic_gates.sv
  - logic_gates_NAND.sv
  - logic_gates_NAND_tb.sv
  - logic_gates_tb.sv
  - master_slave_jk_flip_flop.sv
  - master_slave_jk_flip_flop_tb.sv
  - multiplexer_4to1.sv
  - multiplexer_4to1_tb.sv
  - ripple_carry_adder.sv
  - sr_flip_flop.sv
  - sr_flip_flop_tb.sv
  - t_flip_flop.sv
  - t_flip_flop_tb.sv
- Project_1.pdf
- README.md
- Project 20_ Sklansky Adder (4-bit).pdf
- Project 21_ Hancarlson Adder.pdf
- 22 Manchester Carry Chain Adder (MCC).pdf
- 23 MODULAR ADDER.pdf
- Project_24 Pipelined Adder.pdf
- 25 Redundant Binary Adder.pdf
- Hybrid Adder (Project 26).pdf
- Project 27_ UNSIGNED BINARY ADDER .pdf
- Project 28_ Carry Save Array Multiplier.pdf
- 29 Wallace Tree Multipler.pdf
- Project_2.pdf
- README.md
- ripple_carry_adder.sv
- ripple_carry_adder_sch.png
- ripple_carry_adder_sim.png
- ripple_carry_adder_syn_sch.png
- ripple_carry_adder_tb.sv
- Project 30_ Dadda Multiplier .pdf
- 31 REDUCED AREA MULTIPLIER.pdf
- Project 32_ Truncated Multiplier.pdf
- 33 Signed Sequential Multilpier.pdf
- Project 34_ Booth Multiplier.pdf
- 35 SIGN RADIX-4 MODIFIED BOOTH MULTIPLIER.pdf
- Project 36_ Fixed Multiplier.pdf
- 37.pdf
- Project 38 _ Signed Multiplier.pdf
- 39 CANONIC SIGNED DIGIT (CSD) MULTIPLIER.pdf
- cla04.sv
- cla_sch.png
- cla_sim.png
- cla_syn.png
- Project_3.pdf
- TB.txt
- Project_ 40 Partial Product Adder Multiplier.pdf
- 41 Look Up Multiplier.pdf
- Project 42_ Fast Fourier Transform Multiplier .pdf
- 43 BINARY MULTIPLIER.pdf
- Project 44_ SIGNED MULTIPLIER.pdf
- 45 Synchronus Multiplier.pdf
- 46 Asynchronous Multiplier.pdf
- 47.pdf
- Project 48_ REDUNDANT BINARY MULTIPLIER.pdf
- Project 49_ Systolic Multiplier.pdf
- 32bitclasch.png
- 32bitclasim.png
- 32bitclasyn.png
- adder32bit_tb.sv
- bclg32.sv
- BCLG_16bit.sv
- cla04.sv
- CLA_16bit.sv
- Project_4.pdf
- Project 50_ Column-Bias Multiplier.pdf
- 51 Multipliers in FPGA.pdf
- PROJECT 52_ DIGIT SERIAL MULTIPLIER.pdf
- Project 53_ Substrate Based Multiplier.pdf
- Project 54_ Integer Divider.pdf
- 55 FRACTIONAL DIVIDER.pdf
- PROJECT 56_ MODULO-N DIVIDER.pdf
- 57 Dynamic Divider.pdf
- 58 Pipeline Divider.pdf
- 59 ADAPTIVE DIVIDER.pdf
- cas04.sv
- csa16.sv
- csa16a.sv
- csasch.png
- csasim.png
- csasyn.png
- Project_5.pdf
- Project 60_ Low Power Divider.pdf
- Project 61_ Programmable Divider .pdf
- Project 62 _ Asynchronous Divider.pdf
- 63 CLOCK RECOVERY DIVIDER.pdf
- Project 64_ Digital Phase Locked Loop Divider.pdf
- project 65 Random access memory.pdf
- Project 66_ High Speed Divider.pdf
- 67 FREQUENCY SYNTHESIZER DIVIDER.pdf
- Projecf 68_ N Stage Divider.pdf
- Project 69_ Dynamic Comparator.pdf
- csea16.sv
- csea16tb.sv
- cseasch.png
- cseasim.png
- cseasyn.png
- Project_6.pdf
- Project 7 Carry Select Adders.pdf
- Project 70_ Latched Comparator.pdf
- Project 71 Sub-threshold.pdf
- Project 72_ Low Voltage Comparator.pdf
- Project 73_ Multi Threshold Comparator .pdf
- Project 74_ Arithmetic Shift Register.pdf
- Project 75 LOGICAL SHIFT REGISTER.pdf
- Project 76_ Barrel Shifter.pdf
- Project 77.pdf
- Project 78_ Programmable Shifter.pdf
- Project 79 SINGLE PRECISION FPU.pdf
- Project 80_ DOUBLE PRECISION FPU.pdf
- Project 81_ Vector FPU .pdf
- Project 82_ Decimal FPU.pdf
- Project 83 HYBRID FPU.pdf
- Project 84_ Traffic Light Controller (TLC).pdf
- Project 85_ Elevator Control System .pdf
- Project 86_ Vending Machine .pdf
- Project 87 SEQUENCE DETECTOR.pdf
- Project 88_ Digital Clock.pdf
- Project 89_ Advanced Binary Counter .pdf
- Brent-Kung Adder.pdf
- Project 90 Moore Machine for Even.pdf
- Project 91 Mealy Machine for Bit.pdf
- Project 92_ Stop watch Controller.pdf
- Project 93_ Temperature Controller .pdf
- Project 94.pdf
- PROJECT 95.pdf
- Project 96_ Automatic Door Controller.pdf
- Project 97_ Packet Transmitter .pdf
- Project 98 Memory Controller FSM.pdf
- Project 99 TOKEN RING ARBITER FSM.pdf
LICENSE
README.md

// repository documentation

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108-RTL-Projects

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