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uart-verilog

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A Verilog implementation of the UART communication protocol.

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- BAUD_ARCH.png
- BAUD_COUNTER_FLOW.png
- FIFO_ARCH.png
- FIFO_FLOW.png
- RECEIVER_ARCH.png
- RX_FSM.png
- TRANSMITTER_ARCH.png
- TX_FSM.png
- uart_baud_gen.v
- uart_fifo.v
- uart_registers.v
- uart_rx.v
- uart_top.v
- uart_tx.v
- uart_baud_gen_tb.v
- uart_fifo_tb.v
- uart_loopback_tb.v
- uart_registers_tb.v
- uart_rx_tb.v
- uart_top_tb.v
- uart_tx_tb.v
README.md

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<h1 align="center">UART-Verilog</h1>

<p align="center">
  <img src="https://img.shields.io/badge/Language-Verilog-blue?style=for-the-badge"/>
  <img src="https://img.shields.io/badge/Domain-Digital_Design-red?style=for-the-badge"/>
  <img src="https://img.shields.io/badge/Style-16550_UART-yellow?style=for-the-badge"/>
  <img src="https://img.shields.io/badge/Topic-FIFO%20%7C%20FSM%20%7C%20Register_Interface-green?style=for-the-badge"/>
</p>

---

## Overview

**UART-Verilog** is a from-scratch, 16550-inspired UART core featuring configurable TX/RX, synchronous FIFOs, CPU-mapped registers, and flexible frame configuration. The project follows a realistic hardware development workflow, with module-level verification, system integration, and debugging of real timing and data-path issues.

### Project Goals

- Build a correct, configurable UART transmit/receive datapath from bit-level FSMs up.
- Wrap it in a 16550-style CPU register interface so it's usable by a real bus master, not just a testbench.
- Make it genuinely configurable — 5–8 data bits, 1–2 stop bits, even parity, break control — driven live from `LCR`, not hardcoded.
- Detect and report the standard UART error conditions (Parity, Framing, Overrun) through `LSR`.
- Verify the whole thing as one integrated system (`uart_top_tb`), not just as isolated unit tests.

---

## Project Structure

```
uart-verilog/
├── rtl/
│   ├── uart_baud_gen.v      # Baud tick generator (16x oversampling tick from a clock divisor)
│   ├── uart_fifo.v          # Generic synchronous FIFO (parameterized depth/width)
│   ├── uart_tx.v            # Transmitter FSM - configurable word length/stop bits/parity/break
│   ├── uart_rx.v            # Receiver FSM - configurable word length/stop bits/parity + error flags
│   ├── uart_registers.v     # CPU-mapped register file - decodes the bus, owns both FIFOs + both engines
│   └── uart_top.v           # Top-level entry point (thin wrapper around uart_registers - see below)
│
├── tb/
│   ├── uart_baud_gen_tb.v   # Unit test - baud generator only
│   ├── uart_fifo_tb.v       # Unit test - FIFO only
│   ├── uart_tx_tb.v         # Unit test - TX engine only
│   ├── uart_rx_tb.v         # Unit test - RX engine only
│   ├── uart_loopback_tb.v   # Integration test - TX/RX engines looped back (pre-register-interface)
│   ├── uart_registers_tb.v  # Integration test - register interface, DLAB, DLL/DLM, THR/RBR, LSR, FCR
│   └── uart_top_tb.v        # Full-system integration test - the canonical, up-to-date testbench
│
├── img/                     # Architecture diagrams (see below)
│
└── README.md
```

> **Note on the `tb/` folder:** `uart_top_tb.v` is the actively-maintained, comprehensive testbench and the one to run for anything beyond a single module. The earlier per-module testbenches (`uart_tx_tb.v`, `uart_rx_tb.v`, `uart_loopback_tb.v`, `uart_registers_tb.v`) were the right tool while building each piece incrementally, but they test interfaces that have since changed (e.g. `uart_tx`/`uart_rx` gained four new configuration ports, `uart_loopback_tb.v` predates the register interface entirely) and have **not** been updated to match.

## Architecture

```text
                         CPU / Bus Interface
                                  │
                                  ▼
                       ┌─────────────────────┐
                       │   UART Registers    │
                       │  LCR DLL DLM FCR    │
                       │  LSR SCR            │
                       └──────────┬──────────┘
                                  │
                    ┌─────────────┴─────────────┐
                    ▼                           ▼
              ┌───────────┐               ┌───────────┐
              │  TX FIFO  │               │  RX FIFO  │
              └─────┬─────┘               └─────▲─────┘
                    ▼                           │
              ┌───────────┐               ┌─────┴─────┐
              │ TX Engine │               │ RX Engine │
              └─────┬─────┘               └─────▲─────┘
                    ▼                           │
                   TXD                          RXD
                    │                           │
                    └────── Baud Generator ─────┘
```

The system is a single CPU-facing register file (`uart_registers`, wrapped by `uart_top`) sitting on top of four independently-verified building blocks: a baud generator, two FIFOs, and the TX/RX FSMs.

| Diagram | What it shows |
|---|---|
| `img/BAUD_ARCH.png` | Baud generator block diagram |
| `img/BAUD_COUNTER_FLOW.png` | Baud divisor counter flow |
| `img/FIFO_ARCH.png` | FIFO block diagram (pointers, count, flags) |
| `img/FIFO_FLOW.png` | FIFO read/write control flow |
| `img/TRANSMITTER_ARCH.png` | TX datapath (shift register, dispatcher, output mux) |
| `img/TX_FSM.png` | TX FSM state diagram (IDLE → START → DATA → PARITY → STOP) |
| `img/RECEIVER_ARCH.png` | RX datapath (synchronizer, shift register, oversampling) |
| `img/RX_FSM.png` | RX FSM state diagram, mirroring TX with center-bit sampling |

---

## Key Components

### `uart_baud_gen.v`
Free-running counter that pulses `baud_tick` once every `dvsr+1` clock cycles, where `dvsr = {DLM, DLL}` comes straight from the register file. This tick is the shared timebase both TX and RX use for bit timing (16 ticks per UART bit, oversampled for RX center-bit sampling).

### `uart_fifo.v`
Generic, depth/width-parameterized synchronous FIFO. Both TX and RX use two instances of it (depth 16, width 8). Its read port is **registered** — `r_data` reflects a `read_op` request one clock cycle later, not the same cycle. This single fact is the root cause behind two of the more interesting bugs found during development (see below).

### `uart_tx.v`
Transmitter FSM: `IDLE → START → DATA → [PARITY] → STOP → IDLE`. Word length (5–8 bits), stop-bit count (1–2), parity (even, optional), and break are all runtime-configurable and latched once per frame so a mid-frame LCR change can't corrupt an in-flight transmission. A `start_pending` latch means a new byte requested while the engine is still finishing the previous frame is never silently dropped.

### `uart_rx.v`
Mirrors the TX FSM, with a 2-flop synchronizer on `Rx` and center-of-bit sampling (tick 7 of 16) for noise margin. As of Phase 12, a byte is **always** delivered on frame completion — a bad stop bit no longer silently drops the byte, it's delivered *with* `rx_framing_error` flagged, matching real 16550 behavior.

### `uart_registers.v`
The CPU-facing register file. Owns the baud generator, both FIFOs, and both engines. Two purpose-built pieces of glue logic exist specifically to handle the FIFO's registered-read latency:
- **TX dispatcher** — a 2-state Mealy FSM that issues `read_op`, waits exactly one cycle for `r_data` to become valid, then hands the byte to the TX engine via `tx_start`.
- **RBR shadow register** — since the CPU read bus is combinational (`rd_data` must be valid the same cycle as `rd_en`), the oldest FIFO entry is continuously pre-fetched into a shadow register ahead of time, so a CPU read never has to wait on the FIFO's own latency.

### `uart_top.v`
Thin pass-through wrapper around `uart_registers` — see the Phase 15 note above.

---

## What Was Skipped

* **Odd parity**

* **Interrupts (IER/IIR), Modem Control (MCR/MSR), DMA**

* **FCR bit 0 (FIFO Enable)**

* **Sticky/read-to-clear LSR error bits**

* **Break Interrupt (LSR bit 4)**

---

## Running the Testbench

### Files needed in your ModelSim project
All of `rtl/*.v` plus `tb/uart_top_tb.v`. The per-module testbenches are independent of this and don't need to be compiled alongside it.

### Compile & run
```tcl
vlog rtl/uart_baud_gen.v rtl/uart_fifo.v rtl/uart_tx.v rtl/uart_rx.v rtl/uart_registers.v rtl/uart_top.v tb/uart_top_tb.v
vsim uart_top_tb
run -all
```

### What to expect
- A final line: `RESULTS: <N> PASS / 0 FAIL / 1 SKIP` (the one SKIP is the documented odd-parity gap, not a failure).
- One `SKIP:` line printed mid-run for odd parity, matching the table above.
- Several `>>> STOP CHECK` / `>>> RX DONE GENERATED` debug lines from `uart_rx.v` throughout — these are intentional, left in from earlier debugging, and safe to ignore or strip out during cleanup.

---

<p align="center"><i>UART-Verilog — a 16550-style UART core built and verified from the bit level up, one integration bug at a time.</i></p>