Gati
Gati Accelerates Your CNN Algorithms!
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- 2x2.jpg
- 3channel-image.png
- 3x3-0-indexed.jpg
- 3x3-4x4.jpg
- 3x3.jpg
- Activation.png
- adder_tree.svg
- Bias Addition.png
- Bias_Addition.png
- Bias_Addition_1.png
- birdseyearch.jpg
- channel-first.drawio
- channel-first.svg
- chw.png
- concat_block_diag.svg
- concat_eltwise.svg
- concat_memory.svg
- config.png
- config_block.pdf
- Configuration_Block.jpg
- DDRaccess.jpg
- depthwise.jpg
- dispatch.png
- dram_ctrl.svg
- dwp.png
- dwp_packet.png
- eltwise_op.svg
- FC_Engine.png
- Flattening 9,4,4.png
- Flattening.png
- Flattening_9,4,4.png
- Generalized_Pool.png
- hwc.png
- Im2Col_cs231n.png
- IoU.png
- mega_pool.svg
- memlayout1.jpg
- memlayout2.jpg
- memlayout3.jpg
- Memory_Controller.jpg
- no_padding_no_strides.gif
- non-3x3-kernels.jpg
- Overview.png
- pointwise.jpg
- pooling-network.jpg
- Quantization.png
- Quantization1.png
- reshape_transpose.svg
- resize.svg
- resnet50-float-distrib.png
- sa_engine.svg
- sa_pe.svg
- Sigmoid.svg
- slave.png
- Slave_example.jpg
- store.drawio
- store.png
- tanh.png
- vaaman-arch.svg
- vgg16-12.svg
- vgg16_onnx_weight_densities.png
- conv.txt
- fc.txt
- gen.sh
- gen_all.sh
- gen_cpp.sh
- gen_cpp_defines.sh
- gen_cpp_tables.sh
- gen_verilog_defines.sh
- inst.rst
- meta.txt
- output.txt
- start.txt
- tail.txt
- zero.txt
- adder_tree.rst
- alignment.rst
- concat.rst
- conf.py
- configuration-block.rst
- dispatcher.rst
- DRAM-controller.rst
- dram.rst
- DWP.rst
- eltwise_op.rst
- gati.rst
- index.rst
- input_blocks.rst
- introduction.rst
- mega_pool.rst
- networks.rst
- nms.rst
- overview.rst
- quantization.rst
- references.rst
- refs.bib
- reshape_transpose.rst
- Resize.rst
- sa.rst
- Sigmoid_tanh_block.rst
- store.md
- Linting_using_verilator.md
- make.bat
- Makefile
- NewBoard.md
- README.md
- RELEASE.txt
- verilog_style_guide.md
- adder.v
- top_adder_tree.v
- controller.v
- OP_Concat.v
- OP_CONV.v
- OP_EltWise.v
- OP_FC.v
- OP_Outputblock.v
- OP_POOL.v
- OP_ReshapeTranspose.v
- OP_Resize.v
- OP_Tailblock.v
- top_master.v
- top_master_slave_integrate.v
- arch_functions.vh
- arch_param.vh
- demux_param.v
- demux_param1.v
- fifo_valid.v
- gen_hardware.vh
- instructions.vh
- interconnect_dram_data_aligner.v
- memory_valid.v
- mux_param.v
- operator_fifo_wren_ctrl.v
- portid.vh
- simple_dpram.v
- vector_mux_param.v
- concat_controller.v
- concat_length_switcher.v
- concat_req_address_switch.v
- request_controller_concat.v
- top_concat.v
- controller_inst_q.v
- ctrl_ack.v
- ctrl_dram_req.v
- inst_q.v
- inst_read_ctrl.v
- sync_fifo_config.v
- top_config_blk.v
- demux.v
- rden_mux.v
- top_fifo_sharing.v
- weight_ff_array.v
- bram_bank_array.v
- bram_rden_ctrl.v
- bram_wren_ctrl.v
- conv_output_reorder.v
- onehot_to_bin.v
- output_mux.v
- top_flattening.v
- Accumulator_sel_ctrler.v
- CONV_ip_data_handler.v
- FC_OP_Data_reorder.v
- fifo_sharing_weight_wren_ctrl.v
- im2col_start_ctrler.v
- interconnect.v
- interconnect_sa_pool.v
- iteration_cnt_new.v
- mega_block_start_cntrl.v
- Mem_read_ctrl.v
- Mem_write_ctrl.v
- op_psum_rden.v
- quant_interconnect.v
- sa_start_stall_ctrl.v
- Tail_done_gen.v
- data_rd_ctrl.v
- dispatch_flag_check.v
- mem_req_ctrl.v
- mipi_formatter.v
- request_generator.v
- top_dispatch.v
- op_write_req_block.v
- dram_fifo.v
- controller.v
- conv_output_reorder_EW.v
- element_wise_op.v
- top_element_wise.v
- accumulator.v
- top_fc.v
- weight_ff_rden.v
- counter_demux.v
- counter_pooling_second.v
- counter_rowwise_columnwise.v
- demux_for_fifo1.v
- gen_mod_op.v
- generalized_pool.v
- mod_op.v
- mux_final_pool.v
- pooling_first_stage.v
- pooling_second_stage.v
- README.md
- top_max.v
- im2col_buffer_write.v
- top_buffer.v
- bound_generation.v
- delay_reg.v
- gen_mod_op.v
- index_coordinate.v
- mod_op.v
- psuedo_index_cor.v
- stride_block.v
- stride_mod.v
- top_im2col.v
- component.pickle
- graph.pickle
- bram_decompose.vh
- bram_ini.vh
- init_hex.mem
- sdpram.v
- sdpram_define.vh
- sdpram_tmpl.v
- sdpram_tmpl.vhd
- settings.json
- component.pickle
- graph.pickle
- settings.json
- sync_fifo.v
- sync_fifo_define.vh
- sync_fifo_tmpl.v
- sync_fifo_tmpl.vhd
- gen_global_avg_pool.v
- global_avg_pool.v
- image_fifo_array_rden_pool.v
- Pool_PE.v
- Pool_PE_array.v
- top_pool_engine.v
- data_fifo.v
- data_fifo_define.vh
- data_fifo_tmpl.v
- data_fifo_tmpl.vhd
- settings.json
- Axi4FullDeplex.v
- ddr_reset_sequencer.v
- onehot_to_bin.v
- Port_controller.v
- Port_ctrl_gen.v
- Rd_ctrl.v
- RD_ID_Manager.v
- Req_Manager.v
- Req_Queue_gen.v
- RR_ARB.v
- tags
- Top_Axi.v
- Top_DRAM_controller.v
- Wr_ctrl.v
- WR_ID_Manager.v
- counters.v
- data_mem_ctrl.v
- debug_top.v
- dram_wr_ctrl.v
- fifo_wr_ctrl.v
- image_fifo_array_async.v
- mipi_ctrl_top.v
- pulse_gen.v
- sync_fifo.v
- wr_req_ctrl.v
- top_mux.v
- demux_controller_sel_op.v
- Demux_param.v
- acc_fifo_rden.v
- adder.v
- bias_controller.v
- new_controller.v
- top_bias_block.v
- top_bias_fc.v
- top_output_block.v
- vector_mux.v
- vector_mux_param.v
- mul_shift.v
- top_quant_gen.v
- relu_w_gen.v
- request_controller_accumulator.v
- request_controller_bias.v
- request_controller_EltWise.v
- request_controller_FC.v
- request_controller_FCbias.v
- request_controller_img.v
- request_controller_img_pool.v
- request_controller_weights.v
- bram_rd_ctrl.v
- bram_wr_ctrl.v
- delay_reg_rt.v
- DRAM_read_requestor.v
- fifo_wr_ctrl_rt.v
- gen_bram.v
- gen_fifo.v
- top_reshape_transpose.v
- TOP_W_BRAM.v
- bram_rd_ctrl_resize.v
- bram_wr_ctrl_resize.v
- dram_fifo_resize.v
- gen_bram_resize.v
- gen_top_resize.v
- top_resize_block.v
- append_dv.v
- delay_reg.v
- dsp_pe_blocks.v
- dsp_pe_grid.v
- fifo_array.v
- image_fifo_array.v
- image_fifo_array_rden.v
- lut_pe_block.v
- lut_pe_grid.v
- pulse_gen.v
- rden_delay_reg.v
- README.md
- sa_engine_dsp.v
- sa_engine_lut.v
- seperate_psum_dv.v
- top_sa.v
- weight_fifo_array_rden.v
- generate_shift_register.v
- mux.v
- register.v
- top_shift_register.v
- input_range_decoder.v
- interpolation_points.txt
- interpolator_engine.v
- slope_values.txt
- tanh_interpolator_engine.v
- tanh_values.txt
- top_Tanh_Sigmoid_Engine.v
- top_zero.v
- zero_padder.v
- dram_data_aligner.v
- rah_gati.v
- top_conv_pool_fc.v
- top_gati.v
- top_tailblock.v
- sa_tb.v
- tb_mul_shift_des2.v
- tb_right_shifter_des2.v
- tb_relu_0.v
- tb_ReLU_6.v
- tb_relu_8.v
- tb_upsample.v
- testbench.v
- top_design.v
- tanh_sigmoid_input.txt
- tanh_sigmoid_output.txt
- tb_tanh_sigmoid.v
- tb_tanh_sigmoid_elementwise.v
- tb_top_im2col.v
- CONTRIBUTION.md
- LICENSE.md
- README.md
- VERSION.txt
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